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Commit 8c0b4fd8 authored by Peter Ujfalusi's avatar Peter Ujfalusi Committed by Tony Lindgren
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ARM: dts: dra7xx-clocks: Correct mcasp2_ahclkx_mux bit-shift 



The correct bit is 24 for AHCLKX.

Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent ada76576

arch/arm/boot/dts/dra7xx-clocks.dtsi

+1 −1
Original line number Original line Diff line number Diff line
@@ -1640,7 +1640,7 @@ 
		#clock-cells = <0>;

		#clock-cells = <0>;

		compatible = "ti,mux-clock";

		compatible = "ti,mux-clock";

		clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;

		clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;

		ti,bit-shift = <28>;

		ti,bit-shift = <24>;

		reg = <0x1860>;

		reg = <0x1860>;

	};

	};