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Commit 8bcc2795 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: hw state readout for i9xx dplls 



In addition to existing stuff we also need to track DPLL_MD on gen4
and vlv. This is prep work so that we can move the dpll enable
sequence out from the ->mode_set callback into the crtc enabling
functions.

Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 952735ee

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -144,6 +144,7 @@ enum intel_dpll_id { 


struct intel_dpll_hw_state {

	uint32_t dpll;

	uint32_t dpll_md;

	uint32_t fp0;

	uint32_t fp1;

};

drivers/gpu/drm/i915/intel_display.c

+20 −0
Original line number Diff line number Diff line
@@ -4272,14 +4272,17 @@ static void i9xx_update_pll_dividers(struct intel_crtc *crtc, 
	}



	I915_WRITE(FP0(pipe), fp);

	crtc->config.dpll_hw_state.fp0 = fp;



	crtc->lowfreq_avail = false;

	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&

	    reduced_clock && i915_powersave) {

		I915_WRITE(FP1(pipe), fp2);

		crtc->config.dpll_hw_state.fp1 = fp2;

		crtc->lowfreq_avail = true;

	} else {

		I915_WRITE(FP1(pipe), fp);

		crtc->config.dpll_hw_state.fp1 = fp;

	}

}
@@ -4457,6 +4460,8 @@ static void vlv_update_pll(struct intel_crtc *crtc) 
		dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;



	dpll |= DPLL_VCO_ENABLE;

	crtc->config.dpll_hw_state.dpll = dpll;



	I915_WRITE(DPLL(pipe), dpll);

	POSTING_READ(DPLL(pipe));

	udelay(150);
@@ -4466,6 +4471,8 @@ static void vlv_update_pll(struct intel_crtc *crtc) 


	dpll_md = (crtc->config.pixel_multiplier - 1)

		<< DPLL_MD_UDI_MULTIPLIER_SHIFT;

	crtc->config.dpll_hw_state.dpll_md = dpll_md;



	I915_WRITE(DPLL_MD(pipe), dpll_md);

	POSTING_READ(DPLL_MD(pipe));
@@ -4544,6 +4551,8 @@ static void i9xx_update_pll(struct intel_crtc *crtc, 
		dpll |= PLL_REF_INPUT_DREFCLK;



	dpll |= DPLL_VCO_ENABLE;

	crtc->config.dpll_hw_state.dpll = dpll;



	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);

	POSTING_READ(DPLL(pipe));

	udelay(150);
@@ -4564,6 +4573,8 @@ static void i9xx_update_pll(struct intel_crtc *crtc, 
	if (INTEL_INFO(dev)->gen >= 4) {

		u32 dpll_md = (crtc->config.pixel_multiplier - 1)

			<< DPLL_MD_UDI_MULTIPLIER_SHIFT;

		crtc->config.dpll_hw_state.dpll_md = dpll_md;



		I915_WRITE(DPLL_MD(pipe), dpll_md);

	} else {

		/* The pixel multiplier can only be updated once the
@@ -4608,6 +4619,8 @@ static void i8xx_update_pll(struct intel_crtc *crtc, 
		dpll |= PLL_REF_INPUT_DREFCLK;



	dpll |= DPLL_VCO_ENABLE;

	crtc->config.dpll_hw_state.dpll = dpll;



	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);

	POSTING_READ(DPLL(pipe));

	udelay(150);
@@ -4964,6 +4977,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 
		pipe_config->pixel_multiplier =

			((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)

			 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;

		pipe_config->dpll_hw_state.dpll_md = tmp;

	} else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {

		tmp = I915_READ(DPLL(crtc->pipe));

		pipe_config->pixel_multiplier =
@@ -4975,6 +4989,11 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 
		 * function. */

		pipe_config->pixel_multiplier = 1;

	}

	pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));

	if (!IS_VALLEYVIEW(dev)) {

		pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));

		pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));

	}



	return true;

}
@@ -8126,6 +8145,7 @@ intel_pipe_config_compare(struct drm_device *dev, 


	PIPE_CONF_CHECK_I(shared_dpll);

	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);

	PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);

	PIPE_CONF_CHECK_X(dpll_hw_state.fp0);

	PIPE_CONF_CHECK_X(dpll_hw_state.fp1);