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Commit 8bc6d05b authored by David Daney's avatar David Daney Committed by Ralf Baechle
Browse files

MIPS: Read watch registers with interrupts disabled. 



If a context switch occurred between the watch exception and reading the
watch registers, it would be possible for the new process to corrupt their
state.  Enabling interrupts only after the watch registers are read avoids
this race.

Signed-off-by: default avatarDavid Daney <ddaney@caviumnetworks.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 7adbedaf

arch/mips/kernel/genex.S

+5 −1
Original line number Diff line number Diff line
@@ -458,7 +458,11 @@ NESTED(nmi_handler, PT_SIZE, sp) 
	BUILD_HANDLER fpe fpe fpe silent		/* #15 */

	BUILD_HANDLER mdmx mdmx sti silent		/* #22 */

#ifdef 	CONFIG_HARDWARE_WATCHPOINTS

	BUILD_HANDLER watch watch sti silent		/* #23 */

	/*

	 * For watch, interrupts will be enabled after the watch

	 * registers are read.

	 */

	BUILD_HANDLER watch watch cli silent		/* #23 */

#else

	BUILD_HANDLER watch watch sti verbose		/* #23 */

#endif

arch/mips/kernel/traps.c

+7 −1
Original line number Diff line number Diff line
@@ -944,6 +944,9 @@ asmlinkage void do_mdmx(struct pt_regs *regs) 
	force_sig(SIGILL, current);

}



/*

 * Called with interrupts disabled.

 */

asmlinkage void do_watch(struct pt_regs *regs)

{

	u32 cause;
@@ -963,9 +966,12 @@ asmlinkage void do_watch(struct pt_regs *regs) 
	 */

	if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {

		mips_read_watch_registers();

		local_irq_enable();

		force_sig(SIGTRAP, current);

	} else

	} else {

		mips_clear_watch_registers();

		local_irq_enable();

	}

}



asmlinkage void do_mcheck(struct pt_regs *regs)