usb:hsotg:samsung: Comments reorganization and cleanup

/* linux/drivers/usb/gadget/s3c-hsotg.c

/**

 * linux/drivers/usb/gadget/s3c-hsotg.c

 *

 * Copyright (c) 2011 Samsung Electronics Co., Ltd.

 *		http://www.samsung.com

	"vusb_a",		/* analog USB supply, 1.1V */

};

/* EP0_MPS_LIMIT

/*

 * EP0_MPS_LIMIT

 *

 * Unfortunately there seems to be a limit of the amount of data that can

 * be transferred by IN transactions on EP0. This is either 127 bytes or 3

	int timeout;

	u32 val;

	/* the ryu 2.6.24 release ahs

	   writel(0x1C0, hsotg->regs + S3C_GRXFSIZ);

	   writel(S3C_GNPTXFSIZ_NPTxFStAddr(0x200) |

		S3C_GNPTXFSIZ_NPTxFDep(0x1C0),

		hsotg->regs + S3C_GNPTXFSIZ);

	*/

	/* set FIFO sizes to 2048/1024 */

	writel(2048, hsotg->regs + S3C_GRXFSIZ);

	       S3C_GNPTXFSIZ_NPTxFDep(1024),

	       hsotg->regs + S3C_GNPTXFSIZ);

	/* arange all the rest of the TX FIFOs, as some versions of this

	/*

	 * arange all the rest of the TX FIFOs, as some versions of this

	 * block have overlapping default addresses. This also ensures

	 * that if the settings have been changed, then they are set to

	 * known values. */

	 * known values.

	 */

	/* start at the end of the GNPTXFSIZ, rounded up */

	addr = 2048 + 1024;

	size = 768;

	/* currently we allocate TX FIFOs for all possible endpoints,

	 * and assume that they are all the same size. */

	/*

	 * currently we allocate TX FIFOs for all possible endpoints,

	 * and assume that they are all the same size.

	 */

	for (ep = 1; ep <= 15; ep++) {

		val = addr;

		writel(val, hsotg->regs + S3C_DPTXFSIZn(ep));

	}

	/* according to p428 of the design guide, we need to ensure that

	 * all fifos are flushed before continuing */

	/*

	 * according to p428 of the design guide, we need to ensure that

	 * all fifos are flushed before continuing

	 */

	writel(S3C_GRSTCTL_TxFNum(0x10) | S3C_GRSTCTL_TxFFlsh |

	       S3C_GRSTCTL_RxFFlsh, hsotg->regs + S3C_GRSTCTL);

		int size_left;

		int size_done;

		/* work out how much data was loaded so we can calculate

		 * how much data is left in the fifo. */

		/*

		 * work out how much data was loaded so we can calculate

		 * how much data is left in the fifo.

		 */

		size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);

		/* if shared fifo, we cannot write anything until the

		/*

		 * if shared fifo, we cannot write anything until the

		 * previous data has been completely sent.

		 */

		if (hs_ep->fifo_load != 0) {

	dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, mps %d\n",

		 __func__, gnptxsts, can_write, to_write, hs_ep->ep.maxpacket);

	/* limit to 512 bytes of data, it seems at least on the non-periodic

	/*

	 * limit to 512 bytes of data, it seems at least on the non-periodic

	 * FIFO, requests of >512 cause the endpoint to get stuck with a

	 * fragment of the end of the transfer in it.

	 */

	if (can_write > 512)

		can_write = 512;

	/* limit the write to one max-packet size worth of data, but allow

	/*

	 * limit the write to one max-packet size worth of data, but allow

	 * the transfer to return that it did not run out of fifo space

	 * doing it. */

	 * doing it.

	 */

	if (to_write > hs_ep->ep.maxpacket) {

		to_write = hs_ep->ep.maxpacket;

		to_write = can_write;

		pkt_round = to_write % hs_ep->ep.maxpacket;

		/* Not sure, but we probably shouldn't be writing partial

		 * packets into the FIFO, so round the write down to an

		/*

		 * Round the write down to an

		 * exact number of packets.

		 *

		 * Note, we do not currently check to see if we can ever

		if (pkt_round)

			to_write -= pkt_round;

		/* enable correct FIFO interrupt to alert us when there

		 * is more room left. */

		/*

		 * enable correct FIFO interrupt to alert us when there

		 * is more room left.

		 */

		s3c_hsotg_en_gsint(hsotg,

				   periodic ? S3C_GINTSTS_PTxFEmp :

	maxpkt--;

	maxsize--;

	/* constrain by packet count if maxpkts*pktsize is greater

	 * than the length register size. */

	/*

	 * constrain by packet count if maxpkts*pktsize is greater

	 * than the length register size.

	 */

	if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)

		maxsize = maxpkt * hs_ep->ep.maxpacket;

		epsize = 0;

	if (index != 0 && ureq->zero) {

		/* test for the packets being exactly right for the

		 * transfer */

		/*

		 * test for the packets being exactly right for the

		 * transfer

		 */

		if (length == (packets * hs_ep->ep.maxpacket))

			packets++;

	if (using_dma(hsotg) && !continuing) {

		unsigned int dma_reg;

		/* write DMA address to control register, buffer already

		 * synced by s3c_hsotg_ep_queue().  */

		/*

		 * write DMA address to control register, buffer already

		 * synced by s3c_hsotg_ep_queue().

		 */

		dma_reg = dir_in ? S3C_DIEPDMA(index) : S3C_DOEPDMA(index);

		writel(ureq->dma, hsotg->regs + dma_reg);

	dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);

	writel(ctrl, hsotg->regs + epctrl_reg);

	/* set these, it seems that DMA support increments past the end

	/*

	 * set these, it seems that DMA support increments past the end

	 * of the packet buffer so we need to calculate the length from

	 * this information. */

	 * this information.

	 */

	hs_ep->size_loaded = length;

	hs_ep->last_load = ureq->actual;

		s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);

	}

	/* clear the INTknTXFEmpMsk when we start request, more as a aide

	 * to debugging to see what is going on. */

	/*

	 * clear the INTknTXFEmpMsk when we start request, more as a aide

	 * to debugging to see what is going on.

	 */

	if (dir_in)

		writel(S3C_DIEPMSK_INTknTXFEmpMsk,

		       hsotg->regs + S3C_DIEPINT(index));

	/* Note, trying to clear the NAK here causes problems with transmit

	 * on the S3C6400 ending up with the TXFIFO becoming full. */

	/*

	 * Note, trying to clear the NAK here causes problems with transmit

	 * on the S3C6400 ending up with the TXFIFO becoming full.

	 */

	/* check ep is enabled */

	if (!(readl(hsotg->regs + epctrl_reg) & S3C_DxEPCTL_EPEna))

		 ctrl->bRequest, ctrl->bRequestType,

		 ctrl->wValue, ctrl->wLength);

	/* record the direction of the request, for later use when enquing

	 * packets onto EP0. */

	/*

	 * record the direction of the request, for later use when enquing

	 * packets onto EP0.

	 */

	ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0;

	dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in);

	/* if we've no data with this request, then the last part of the

	 * transaction is going to implicitly be IN. */

	/*

	 * if we've no data with this request, then the last part of the

	 * transaction is going to implicitly be IN.

	 */

	if (ctrl->wLength == 0)

		ep0->dir_in = 1;

			dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);

	}

	/* the request is either unhandlable, or is not formatted correctly

	/*

	 * the request is either unhandlable, or is not formatted correctly

	 * so respond with a STALL for the status stage to indicate failure.

	 */

		dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);

		reg = (ep0->dir_in) ? S3C_DIEPCTL0 : S3C_DOEPCTL0;

		/* S3C_DxEPCTL_Stall will be cleared by EP once it has

		 * taken effect, so no need to clear later. */

		/*

		 * S3C_DxEPCTL_Stall will be cleared by EP once it has

		 * taken effect, so no need to clear later.

		 */

		ctrl = readl(hsotg->regs + reg);

		ctrl |= S3C_DxEPCTL_Stall;

			"written DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",

			ctrl, reg, readl(hsotg->regs + reg));

		/* don't believe we need to anything more to get the EP

		 * to reply with a STALL packet */

		/*

		 * don't believe we need to anything more to get the EP

		 * to reply with a STALL packet

		 */

	}

}

	ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC);

	if (ret < 0) {

		dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);

		/* Don't think there's much we can do other than watch the

		 * driver fail. */

		/*

		 * Don't think there's much we can do other than watch the

		 * driver fail.

		 */

	}

}

	dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",

		hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);

	/* only replace the status if we've not already set an error

	 * from a previous transaction */

	/*

	 * only replace the status if we've not already set an error

	 * from a previous transaction

	 */

	if (hs_req->req.status == -EINPROGRESS)

		hs_req->req.status = result;

	if (using_dma(hsotg))

		s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req);

	/* call the complete request with the locks off, just in case the

	 * request tries to queue more work for this endpoint. */

	/*

	 * call the complete request with the locks off, just in case the

	 * request tries to queue more work for this endpoint.

	 */

	if (hs_req->req.complete) {

		spin_unlock(&hs_ep->lock);

		spin_lock(&hs_ep->lock);

	}

	/* Look to see if there is anything else to do. Note, the completion

	/*

	 * Look to see if there is anything else to do. Note, the completion

	 * of the previous request may have caused a new request to be started

	 * so be careful when doing this. */

	 * so be careful when doing this.

	 */

	if (!hs_ep->req && result >= 0) {

		restart = !list_empty(&hs_ep->queue);

		__func__, to_read, max_req, read_ptr, hs_req->req.length);

	if (to_read > max_req) {

		/* more data appeared than we where willing

		/*

		 * more data appeared than we where willing

		 * to deal with in this request.

		 */

	hs_req->req.actual += to_read;

	to_read = DIV_ROUND_UP(to_read, 4);

	/* note, we might over-write the buffer end by 3 bytes depending on

	 * alignment of the data. */

	/*

	 * note, we might over-write the buffer end by 3 bytes depending on

	 * alignment of the data.

	 */

	readsl(fifo, hs_req->req.buf + read_ptr, to_read);

	spin_unlock(&hs_ep->lock);

	if (using_dma(hsotg)) {

		unsigned size_done;

		/* Calculate the size of the transfer by checking how much

		/*

		 * Calculate the size of the transfer by checking how much

		 * is left in the endpoint size register and then working it

		 * out from the amount we loaded for the transfer.

		 *

		dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",

			__func__, req->actual, req->length);

		/* todo - what should we return here? there's no one else

		 * even bothering to check the status. */

		/*

		 * todo - what should we return here? there's no one else

		 * even bothering to check the status.

		 */

	}

	if (epnum == 0) {

	hs_ep->ep.maxpacket = mps;

	/* update both the in and out endpoint controldir_ registers, even

	 * if one of the directions may not be in use. */

	/*

	 * update both the in and out endpoint controldir_ registers, even

	 * if one of the directions may not be in use.

	 */

	reg = readl(regs + S3C_DIEPCTL(ep));

	reg &= ~S3C_DxEPCTL_MPS_MASK;

		return;

	}

	/* Calculate the size of the transfer by checking how much is left

	/*

	 * Calculate the size of the transfer by checking how much is left

	 * in the endpoint size register and then working it out from

	 * the amount we loaded for the transfer.

	 *

			__func__, readl(hsotg->regs + epctl_reg),

			readl(hsotg->regs + epsiz_reg));

		/* we get OutDone from the FIFO, so we only need to look

		 * at completing IN requests here */

		/*

		 * we get OutDone from the FIFO, so we only need to look

		 * at completing IN requests here

		 */

		if (dir_in) {

			s3c_hsotg_complete_in(hsotg, hs_ep);

			if (idx == 0 && !hs_ep->req)

				s3c_hsotg_enqueue_setup(hsotg);

		} else if (using_dma(hsotg)) {

			/* We're using DMA, we need to fire an OutDone here

			 * as we ignore the RXFIFO. */

			/*

			 * We're using DMA, we need to fire an OutDone here

			 * as we ignore the RXFIFO.

			 */

			s3c_hsotg_handle_outdone(hsotg, idx, false);

		}

		dev_dbg(hsotg->dev, "%s: Setup/Timeout\n",  __func__);

		if (using_dma(hsotg) && idx == 0) {

			/* this is the notification we've received a

			/*

			 * this is the notification we've received a

			 * setup packet. In non-DMA mode we'd get this

			 * from the RXFIFO, instead we need to process

			 * the setup here. */

			 * the setup here.

			 */

			if (dir_in)

				WARN_ON_ONCE(1);

		dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);

	if (dir_in) {

		/* not sure if this is important, but we'll clear it anyway

		 */

		/* not sure if this is important, but we'll clear it anyway */

		if (ints & S3C_DIEPMSK_INTknTXFEmpMsk) {

			dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",

				__func__, idx);

	u32 dsts = readl(hsotg->regs + S3C_DSTS);

	int ep0_mps = 0, ep_mps;

	/* This should signal the finish of the enumeration phase

	/*

	 * This should signal the finish of the enumeration phase

	 * of the USB handshaking, so we should now know what rate

	 * we connected at. */

	 * we connected at.

	 */

	dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);

	/* note, since we're limited by the size of transfer on EP0, and

	/*

	 * note, since we're limited by the size of transfer on EP0, and

	 * it seems IN transfers must be a even number of packets we do

	 * not advertise a 64byte MPS on EP0. */

	 * not advertise a 64byte MPS on EP0.

	 */

	/* catch both EnumSpd_FS and EnumSpd_FS48 */

	switch (dsts & S3C_DSTS_EnumSpd_MASK) {

	case S3C_DSTS_EnumSpd_LS:

		hsotg->gadget.speed = USB_SPEED_LOW;

		/* note, we don't actually support LS in this driver at the

		/*

		 * note, we don't actually support LS in this driver at the

		 * moment, and the documentation seems to imply that it isn't

		 * supported by the PHYs on some of the devices.

		 */

	dev_info(hsotg->dev, "new device is %s\n",

		 usb_speed_string(hsotg->gadget.speed));

	/* we should now know the maximum packet size for an

	 * endpoint, so set the endpoints to a default value. */

	/*

	 * we should now know the maximum packet size for an

	 * endpoint, so set the endpoints to a default value.

	 */

	if (ep0_mps) {

		int i;

	spin_lock_irqsave(&ep->lock, flags);

	list_for_each_entry_safe(req, treq, &ep->queue, queue) {

		/* currently, we can't do much about an already

		 * running request on an in endpoint */

		/*

		 * currently, we can't do much about an already

		 * running request on an in endpoint

		 */

		if (ep->req == req && ep->dir_in && !force)

			continue;

	return 0;

}

/**

 * s3c_hsotg_core_init - issue softreset to the core

 * @hsotg: The device state

 *

 * Issue a soft reset to the core, and await the core finishing it.

 */

static void s3c_hsotg_core_init(struct s3c_hsotg *hsotg)

{

	s3c_hsotg_corereset(hsotg);

	if (gintsts & S3C_GINTSTS_NPTxFEmp) {

		dev_dbg(hsotg->dev, "NPTxFEmp\n");

		/* Disable the interrupt to stop it happening again

		/*

		 * Disable the interrupt to stop it happening again

		 * unless one of these endpoint routines decides that

		 * it needs re-enabling */

		 * it needs re-enabling

		 */

		s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);

		s3c_hsotg_irq_fifoempty(hsotg, false);

	}

	if (gintsts & S3C_GINTSTS_RxFLvl) {

		/* note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,

		/*

		 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,

		 * we need to retry s3c_hsotg_handle_rx if this is still

		 * set. */

		 * set.

		 */

		s3c_hsotg_handle_rx(hsotg);

	}

		s3c_hsotg_disconnect(hsotg);

	}

	/* these next two seem to crop-up occasionally causing the core

	/*

	 * these next two seem to crop-up occasionally causing the core

	 * to shutdown the USB transfer, so try clearing them and logging

	 * the occurrence. */

	 * the occurrence.

	 */

	if (gintsts & S3C_GINTSTS_GOUTNakEff) {

		dev_info(hsotg->dev, "GOUTNakEff triggered\n");

		s3c_hsotg_dump(hsotg);

	}

	/* if we've had fifo events, we should try and go around the

	 * loop again to see if there's any point in returning yet. */

	/*

	 * if we've had fifo events, we should try and go around the

	 * loop again to see if there's any point in returning yet.

	 */

	if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)

			goto irq_retry;

	epctrl &= ~(S3C_DxEPCTL_EPType_MASK | S3C_DxEPCTL_MPS_MASK);

	epctrl |= S3C_DxEPCTL_MPS(mps);

	/* mark the endpoint as active, otherwise the core may ignore

	 * transactions entirely for this endpoint */

	/*

	 * mark the endpoint as active, otherwise the core may ignore

	 * transactions entirely for this endpoint

	 */

	epctrl |= S3C_DxEPCTL_USBActEp;

	/* set the NAK status on the endpoint, otherwise we might try and

	/*

	 * set the NAK status on the endpoint, otherwise we might try and

	 * do something with data that we've yet got a request to process

	 * since the RXFIFO will take data for an endpoint even if the

	 * size register hasn't been set.

	case USB_ENDPOINT_XFER_INT:

		if (dir_in) {

			/* Allocate our TxFNum by simply using the index

			/*

			 * Allocate our TxFNum by simply using the index

			 * of the endpoint for the moment. We could do

			 * something better if the host indicates how

			 * many FIFOs we are expecting to use. */

			 * many FIFOs we are expecting to use.

			 */

			hs_ep->periodic = 1;

			epctrl |= S3C_DxEPCTL_TxFNum(index);

		break;

	}

	/* if the hardware has dedicated fifos, we must give each IN EP

	/*

	 * if the hardware has dedicated fifos, we must give each IN EP

	 * a unique tx-fifo even if it is non-periodic.

	 */

	if (dir_in && hsotg->dedicated_fifos)

	return ret;

}

/**

 * s3c_hsotg_ep_disable - disable given endpoint

 * @ep: The endpoint to disable.

 */

static int s3c_hsotg_ep_disable(struct usb_ep *ep)

{

	struct s3c_hsotg_ep *hs_ep = our_ep(ep);

	return false;

}

/**

 * s3c_hsotg_ep_dequeue - dequeue given endpoint

 * @ep: The endpoint to dequeue.

 * @req: The request to be removed from a queue.

 */

static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)

{

	struct s3c_hsotg_req *hs_req = our_req(req);

	return 0;

}

/**

 * s3c_hsotg_ep_sethalt - set halt on a given endpoint

 * @ep: The endpoint to set halt.

 * @value: Set or unset the halt.

 */

static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)

{

	struct s3c_hsotg_ep *hs_ep = our_ep(ep);

/**

 * s3c_hsotg_phy_enable - enable platform phy dev

 *

 * @param: The driver state

 * @hsotg: The driver state

 *

 * A wrapper for platform code responsible for controlling

 * low-level USB code

/**

 * s3c_hsotg_phy_disable - disable platform phy dev

 *

 * @param: The driver state

 * @hsotg: The driver state

 *

 * A wrapper for platform code responsible for controlling

 * low-level USB code

		hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);

}

/**

 * s3c_hsotg_init - initalize the usb core

 * @hsotg: The driver state

 */

static void s3c_hsotg_init(struct s3c_hsotg *hsotg)

{

	/* unmask subset of endpoint interrupts */

	       hsotg->regs + S3C_GAHBCFG);

}

/**

 * s3c_hsotg_udc_start - prepare the udc for work

 * @gadget: The usb gadget state

 * @driver: The usb gadget driver

 *

 * Perform initialization to prepare udc device and driver

 * to work.

 */

static int s3c_hsotg_udc_start(struct usb_gadget *gadget,

			   struct usb_gadget_driver *driver)

{

	return ret;

}

/**

 * s3c_hsotg_udc_stop - stop the udc

 * @gadget: The usb gadget state

 * @driver: The usb gadget driver

 *

 * Stop udc hw block and stay tunned for future transmissions

 */

static int s3c_hsotg_udc_stop(struct usb_gadget *gadget,

			  struct usb_gadget_driver *driver)

{

	return 0;

}

/**

 * s3c_hsotg_gadget_getframe - read the frame number

 * @gadget: The usb gadget state

 *

 * Read the {micro} frame number

 */

static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget)

{

	return s3c_hsotg_read_frameno(to_hsotg(gadget));

	hs_ep->ep.maxpacket = epnum ? 512 : EP0_MPS_LIMIT;

	hs_ep->ep.ops = &s3c_hsotg_ep_ops;

	/* Read the FIFO size for the Periodic TX FIFO, even if we're

	/*

	 * Read the FIFO size for the Periodic TX FIFO, even if we're

	 * an OUT endpoint, we may as well do this if in future the

	 * code is changed to make each endpoint's direction changeable.

	 */

	ptxfifo = readl(hsotg->regs + S3C_DPTXFSIZn(epnum));

	hs_ep->fifo_size = S3C_DPTXFSIZn_DPTxFSize_GET(ptxfifo) * 4;

	/* if we're using dma, we need to set the next-endpoint pointer

	/*

	 * if we're using dma, we need to set the next-endpoint pointer

	 * to be something valid.

	 */

	dev_info(hsotg->dev, "%s fifos\n",

		 hsotg->dedicated_fifos ? "dedicated" : "shared");

}

/**

 * s3c_hsotg_dump - dump state of the udc