Merge "clk: msm: mdmfermium: Change blsp_uart corners as per frequency plan" (8ae65e26) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/clk/msm/clock-gcc-mdmfermium.c

+12 −12

Original line number	Diff line number	Diff line
		@@ -320,10 +320,10 @@ static struct clk_freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = {
		F( 960000, xo, 10, 1, 2),
		F( 4800000, xo, 4, 0, 0),
		F( 9600000, xo, 2, 0, 0),
		F( 16670000, gpll0, 12, 1, 4),
		F( 16000000, gpll0, 10, 1, 5),
		F( 19200000, xo, 1, 0, 0),
		F( 25000000, gpll0, 16, 1, 2),
		F( 33330000, gpll0, 12, 1, 2),
		F( 50000000, gpll0, 16, 0, 0),
		F_END
		};

		@@ -336,7 +336,7 @@ static struct rcg_clk blsp1_qup2_spi_apps_clk_src = {
		.c = {
		.dbg_name = "blsp1_qup2_spi_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP2(LOWER, 16670000, NOMINAL, 33330000),
		VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
		CLK_INIT(blsp1_qup2_spi_apps_clk_src.c),
		},
		};
		@@ -360,10 +360,10 @@ static struct clk_freq_tbl ftbl_blsp1_qup3_spi_apps_clk_src[] = {
		F( 4800000, xo, 4, 0, 0),
		F( 9600000, xo, 2, 0, 0),
		F( 16000000, gpll0, 10, 1, 5),
		F( 17390000, gpll0, 1, 1, 46),
		F( 18180000, gpll0, 1, 1, 44),
		F( 19200000, xo, 1, 0, 0),
		F( 25000000, gpll0, 16, 1, 2),
		F( 34780000, gpll0, 1, 1, 23),
		F( 36360000, gpll0, 1, 1, 22),
		F_END
		};

		@@ -376,7 +376,7 @@ static struct rcg_clk blsp1_qup3_spi_apps_clk_src = {
		.c = {
		.dbg_name = "blsp1_qup3_spi_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP2(LOWER, 17390000, NOMINAL, 34780000),
		VDD_DIG_FMAX_MAP2(LOWER, 18180000, NOMINAL, 36360000),
		CLK_INIT(blsp1_qup3_spi_apps_clk_src.c),
		},
		};
		@@ -526,7 +526,7 @@ static struct rcg_clk blsp1_uart1_apps_clk_src = {
		.c = {
		.dbg_name = "blsp1_uart1_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
		VDD_DIG_FMAX_MAP2(LOWER, 48480000, NOMINAL, 64000000),
		CLK_INIT(blsp1_uart1_apps_clk_src.c),
		},
		};
		@@ -540,7 +540,7 @@ static struct rcg_clk blsp1_uart2_apps_clk_src = {
		.c = {
		.dbg_name = "blsp1_uart2_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
		VDD_DIG_FMAX_MAP2(LOWER, 48480000, NOMINAL, 64000000),
		CLK_INIT(blsp1_uart2_apps_clk_src.c),
		},
		};
		@@ -554,7 +554,7 @@ static struct rcg_clk blsp1_uart3_apps_clk_src = {
		.c = {
		.dbg_name = "blsp1_uart3_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
		VDD_DIG_FMAX_MAP2(LOWER, 48480000, NOMINAL, 64000000),
		CLK_INIT(blsp1_uart3_apps_clk_src.c),
		},
		};
		@@ -568,7 +568,7 @@ static struct rcg_clk blsp1_uart4_apps_clk_src = {
		.c = {
		.dbg_name = "blsp1_uart4_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
		VDD_DIG_FMAX_MAP2(LOWER, 48480000, NOMINAL, 64000000),
		CLK_INIT(blsp1_uart4_apps_clk_src.c),
		},
		};
		@@ -582,7 +582,7 @@ static struct rcg_clk blsp1_uart5_apps_clk_src = {
		.c = {
		.dbg_name = "blsp1_uart5_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
		VDD_DIG_FMAX_MAP2(LOWER, 48480000, NOMINAL, 64000000),
		CLK_INIT(blsp1_uart5_apps_clk_src.c),
		},
		};
		@@ -596,7 +596,7 @@ static struct rcg_clk blsp1_uart6_apps_clk_src = {
		.c = {
		.dbg_name = "blsp1_uart6_apps_clk_src",
		.ops = &clk_ops_rcg_mnd,
		VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
		VDD_DIG_FMAX_MAP2(LOWER, 48480000, NOMINAL, 64000000),
		CLK_INIT(blsp1_uart6_apps_clk_src.c),
		},
		};