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Commit 8ae561b9 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "clk: msm: clock: Add support for even and odd PLL post divider control"

parents dd8c3321 d4d62ab7

drivers/clk/msm/clock-generic.c

+4 −2
Original line number Diff line number Diff line
@@ -279,6 +279,8 @@ static long __div_round_rate(struct div_data *data, unsigned long rate, 
		if (data->skip_odd_div && (div & 1))

			if (!(data->allow_div_one && (div == 1)))

				continue;

		if (data->skip_even_div && !(div & 1))

			continue;

		req_prate = mult_frac(rate, div, numer);

		prate = clk_round_rate(parent, req_prate);

		if (IS_ERR_VALUE(prate))
@@ -349,7 +351,7 @@ static int div_set_rate(struct clk *c, unsigned long rate) 
	struct div_data *data = &d->data;



	rrate = __div_round_rate(data, rate, c->parent, &div, &new_prate);

	if (rrate != rate)

	if (rrate < rate || rrate > rate + data->rate_margin)

		return -EINVAL;



	/*
@@ -780,7 +782,7 @@ static int mux_div_clk_set_rate(struct clk *c, unsigned long rate) 


	rrate = __mux_div_round_rate(c, rate, &new_parent, &new_div,

							&new_prate);

	if (rrate != rate)

	if (rrate < rate || rrate > rate + md->data.rate_margin)

		return -EINVAL;



	old_parent = c->parent;

drivers/clk/msm/clock-local2.c

+3 −0
Original line number Diff line number Diff line
@@ -1629,7 +1629,10 @@ static void __iomem *mux_clk_list_registers(struct mux_clk *clk, int n, 
static struct div_map postdiv_map[] = {

	{  0x0, 1  },

	{  0x1, 2  },

	{  0x3, 3  },

	{  0x3, 4  },

	{  0x5, 5  },

	{  0x7, 7  },

	{  0x7, 8  },

	{  0xF, 16 },

};

include/linux/clk/msm-clock-generic.h

+1 −0
Original line number Diff line number Diff line
@@ -123,6 +123,7 @@ struct div_data { 
	 * Skip odd dividers since the hardware may not support them.

	 */

	bool skip_odd_div;

	bool skip_even_div;

	bool allow_div_one;

	unsigned int cached_div;

};