Loading Documentation/devicetree/bindings/misc/at24.txt 0 → 100644 +13 −0 Original line number Diff line number Diff line EEPROMs (IIC) compatible with Atmel at24. Required properties: - compatible : "atmel,24c32". - reg: Should contain registers location Additional compatible properties are also allowed. Example: at24@51 { compatible = "atmel,24c32"; reg = <0x51>; }; arch/arm/boot/dts/qcom/msm8996-mtp.dtsi +7 −0 Original line number Diff line number Diff line Loading @@ -836,6 +836,13 @@ status = "ok"; }; &i2c_6 { at24@51 { compatible = "atmel,24c32"; reg = <0x51>; }; }; &i2c_7 { silabs4705@11 { /* SiLabs FM chip, slave id 0x11*/ status = "ok"; Loading arch/arm/boot/dts/qcom/msm8996-pinctrl.dtsi +28 −0 Original line number Diff line number Diff line Loading @@ -436,6 +436,34 @@ }; }; i2c_6 { i2c_6_active: i2c_6_active { mux { pins = "gpio27", "gpio28"; function = "blsp_i2c6"; }; config { pins = "gpio27", "gpio28"; drive-strength = <2>; bias-disable; }; }; i2c_6_sleep: i2c_6_sleep { mux { pins = "gpio27", "gpio28"; function = "blsp_i2c6"; }; config { pins = "gpio27", "gpio28"; drive-strength = <2>; bias-pull-up; }; }; }; i2c_7 { i2c_7_active: i2c_7_active { mux { Loading arch/arm/boot/dts/qcom/msm8996.dtsi +23 −0 Original line number Diff line number Diff line Loading @@ -35,6 +35,7 @@ pci-domain0 = &pcie0; pci-domain1 = &pcie1; pci-domain2 = &pcie2; i2c6 = &i2c_6; i2c7 = &i2c_7; i2c8 = &i2c_8; i2c12 = &i2c_12; Loading Loading @@ -337,6 +338,28 @@ qcom,summing-threshold = <0x10>; }; i2c_6: i2c@757a000 { /* BLSP1 QUP6 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg = <0x757a000 0x1000>; reg-names = "qup_phys_addr"; interrupt-names = "qup_irq"; interrupts = <0 100 0>; dmas = <&dma_blsp1 22 64 0x20000020 0x20>, <&dma_blsp1 23 32 0x20000020 0x20>; dma-names = "tx", "rx"; qcom,master-id = <86>; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, <&clock_gcc clk_gcc_blsp1_qup6_i2c_apps_clk>; pinctrl-names = "i2c_active", "i2c_sleep"; pinctrl-0 = <&i2c_6_active>; pinctrl-1 = <&i2c_6_sleep>; }; i2c_7: i2c@75b5000 { /* BLSP2 QUP1 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; Loading arch/arm64/configs/msm-perf_defconfig +1 −0 Original line number Diff line number Diff line Loading @@ -230,6 +230,7 @@ CONFIG_UID_STAT=y CONFIG_QSEECOM=y CONFIG_HDCP_QSEECOM=y CONFIG_TI_DRV2667=y CONFIG_EEPROM_AT24=y CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_SG=y Loading Loading
Documentation/devicetree/bindings/misc/at24.txt 0 → 100644 +13 −0 Original line number Diff line number Diff line EEPROMs (IIC) compatible with Atmel at24. Required properties: - compatible : "atmel,24c32". - reg: Should contain registers location Additional compatible properties are also allowed. Example: at24@51 { compatible = "atmel,24c32"; reg = <0x51>; };
arch/arm/boot/dts/qcom/msm8996-mtp.dtsi +7 −0 Original line number Diff line number Diff line Loading @@ -836,6 +836,13 @@ status = "ok"; }; &i2c_6 { at24@51 { compatible = "atmel,24c32"; reg = <0x51>; }; }; &i2c_7 { silabs4705@11 { /* SiLabs FM chip, slave id 0x11*/ status = "ok"; Loading
arch/arm/boot/dts/qcom/msm8996-pinctrl.dtsi +28 −0 Original line number Diff line number Diff line Loading @@ -436,6 +436,34 @@ }; }; i2c_6 { i2c_6_active: i2c_6_active { mux { pins = "gpio27", "gpio28"; function = "blsp_i2c6"; }; config { pins = "gpio27", "gpio28"; drive-strength = <2>; bias-disable; }; }; i2c_6_sleep: i2c_6_sleep { mux { pins = "gpio27", "gpio28"; function = "blsp_i2c6"; }; config { pins = "gpio27", "gpio28"; drive-strength = <2>; bias-pull-up; }; }; }; i2c_7 { i2c_7_active: i2c_7_active { mux { Loading
arch/arm/boot/dts/qcom/msm8996.dtsi +23 −0 Original line number Diff line number Diff line Loading @@ -35,6 +35,7 @@ pci-domain0 = &pcie0; pci-domain1 = &pcie1; pci-domain2 = &pcie2; i2c6 = &i2c_6; i2c7 = &i2c_7; i2c8 = &i2c_8; i2c12 = &i2c_12; Loading Loading @@ -337,6 +338,28 @@ qcom,summing-threshold = <0x10>; }; i2c_6: i2c@757a000 { /* BLSP1 QUP6 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg = <0x757a000 0x1000>; reg-names = "qup_phys_addr"; interrupt-names = "qup_irq"; interrupts = <0 100 0>; dmas = <&dma_blsp1 22 64 0x20000020 0x20>, <&dma_blsp1 23 32 0x20000020 0x20>; dma-names = "tx", "rx"; qcom,master-id = <86>; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, <&clock_gcc clk_gcc_blsp1_qup6_i2c_apps_clk>; pinctrl-names = "i2c_active", "i2c_sleep"; pinctrl-0 = <&i2c_6_active>; pinctrl-1 = <&i2c_6_sleep>; }; i2c_7: i2c@75b5000 { /* BLSP2 QUP1 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; Loading
arch/arm64/configs/msm-perf_defconfig +1 −0 Original line number Diff line number Diff line Loading @@ -230,6 +230,7 @@ CONFIG_UID_STAT=y CONFIG_QSEECOM=y CONFIG_HDCP_QSEECOM=y CONFIG_TI_DRV2667=y CONFIG_EEPROM_AT24=y CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_SG=y Loading