Merge tag 'pinctrl-for-v3.13-1' of...

* Abilis TB10x GPIO controller

Required Properties:

- compatible: Should be "abilis,tb10x-gpio"

- reg: Address and length of the register set for the device

- gpio-controller: Marks the device node as a gpio controller.

- #gpio-cells: Should be <2>. The first cell is the pin number and the

  second cell is used to specify optional parameters:

   - bit 0 specifies polarity (0 for normal, 1 for inverted).

- abilis,ngpio: the number of GPIO pins this driver controls.

Optional Properties:

- interrupt-controller: Marks the device node as an interrupt controller.

- #interrupt-cells: Should be <1>. Interrupts are triggered on both edges.

- interrupts: Defines the interrupt line connecting this GPIO controller to

  its parent interrupt controller.

- interrupt-parent: Defines the parent interrupt controller.

GPIO ranges are specified as described in

Documentation/devicetree/bindings/gpio/gpio.txt

Example:

	gpioa: gpio@FF140000 {

		compatible = "abilis,tb10x-gpio";

		interrupt-controller;

		#interrupt-cells = <1>;

		interrupt-parent = <&tb10x_ictl>;

		interrupts = <27 2>;

		reg = <0xFF140000 0x1000>;

		gpio-controller;

		#gpio-cells = <2>;

		abilis,ngpio = <3>;

		gpio-ranges = <&iomux 0 0 0>;

		gpio-ranges-group-names = "gpioa_pins";

	};

contains information structures as follows:

	gpio-range-list ::= <single-gpio-range> [gpio-range-list]

	single-gpio-range ::=

	single-gpio-range ::= <numeric-gpio-range> | <named-gpio-range>

	numeric-gpio-range ::=

			<pinctrl-phandle> <gpio-base> <pinctrl-base> <count>

	named-gpio-range ::= <pinctrl-phandle> <gpio-base> '<0 0>'

	gpio-phandle : phandle to pin controller node.

	gpio-base : Base GPIO ID in the GPIO controller

	pinctrl-base : Base pinctrl pin ID in the pin controller

The "pin controller node" mentioned above must conform to the bindings

described in ../pinctrl/pinctrl-bindings.txt.

In case named gpio ranges are used (ranges with both <pinctrl-base> and

<count> set to 0), the property gpio-ranges-group-names contains one string

for every single-gpio-range in gpio-ranges:

	gpiorange-names-list ::= <gpiorange-name> [gpiorange-names-list]

	gpiorange-name : Name of the pingroup associated to the GPIO range in

			the respective pin controller.

Elements of gpiorange-names-list corresponding to numeric ranges contain

the empty string. Elements of gpiorange-names-list corresponding to named

ranges contain the name of a pin group defined in the respective pin

controller. The number of pins/GPIOs in the range is the number of pins in

that pin group.

Previous versions of this binding required all pin controller nodes that

were referenced by any gpio-ranges property to contain a property named

#gpio-range-cells with value <3>. This requirement is now deprecated.

compatibility reasons, and would still be required even in new device

trees that need to be compatible with older software.

Example:

Example 1:

	qe_pio_e: gpio-controller@1460 {

		#gpio-cells = <2>;

Here, a single GPIO controller has GPIOs 0..9 routed to pin controller

pinctrl1's pins 20..29, and GPIOs 10..19 routed to pin controller pinctrl2's

pins 50..59.

Example 2:

	gpio_pio_i: gpio-controller@14B0 {

		#gpio-cells = <2>;

		compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";

		reg = <0x1480 0x18>;

		gpio-controller;

		gpio-ranges =			<&pinctrl1 0 20 10>,

						<&pinctrl2 10 0 0>,

						<&pinctrl1 15 0 10>,

						<&pinctrl2 25 0 0>;

		gpio-ranges-group-names =	"",

						"foo",

						"",

						"bar";

	};

Here, three GPIO ranges are defined wrt. two pin controllers. pinctrl1 GPIO

ranges are defined using pin numbers whereas the GPIO ranges wrt. pinctrl2

are named "foo" and "bar".

Abilis Systems TB10x pin controller

===================================

Required properties

-------------------

- compatible: should be "abilis,tb10x-iomux";

- reg: should contain the physical address and size of the pin controller's

  register range.

Function definitions

--------------------

Functions are defined (and referenced) by sub-nodes of the pin controller.

Every sub-node defines exactly one function (implying a set of pins).

Every function is associated to one named pin group inside the pin controller

driver and these names are used to associate pin group predefinitions to pin

controller sub-nodes.

Required function definition subnode properties:

  - abilis,function: should be set to the name of the function's pin group.

The following pin groups are available:

  - GPIO ports: gpioa, gpiob, gpioc, gpiod, gpioe, gpiof, gpiog,

                gpioh, gpioi, gpioj, gpiok, gpiol, gpiom, gpion

  - Serial TS input ports: mis0, mis1, mis2, mis3, mis4, mis5, mis6, mis7

  - Parallel TS input ports: mip1, mip3, mip5, mip7

  - Serial TS output ports: mos0, mos1, mos2, mos3

  - Parallel TS output port: mop

  - CI+ port: ciplus

  - CableCard (Mcard) port: mcard

  - Smart card ports: stc0, stc1

  - UART ports: uart0, uart1

  - SPI ports: spi1, spi3

  - JTAG: jtag

All other ports of the chip are not multiplexed and thus not managed by this

driver.

GPIO ranges definition

----------------------

The named pin groups of GPIO ports can be used to define GPIO ranges as

explained in Documentation/devicetree/bindings/gpio/gpio.txt.

Example

-------

iomux: iomux@FF10601c {

	compatible = "abilis,tb10x-iomux";

	reg = <0xFF10601c 0x4>;

	pctl_gpio_a: pctl-gpio-a {

		abilis,function = "gpioa";

	};

	pctl_uart0: pctl-uart0 {

		abilis,function = "uart0";

	};

};

uart@FF100000 {

	compatible = "snps,dw-apb-uart";

	reg = <0xFF100000 0x100>;

	clock-frequency = <166666666>;

	interrupts = <25 1>;

	reg-shift = <2>;

	reg-io-width = <4>;

	pinctrl-names = "default";

	pinctrl-0 = <&pctl_uart0>;

};

gpioa: gpio@FF140000 {

	compatible = "abilis,tb10x-gpio";

	reg = <0xFF140000 0x1000>;

	gpio-controller;

	#gpio-cells = <2>;

	ngpio = <3>;

	gpio-ranges = <&iomux 0 0>;

	gpio-ranges-group-names = "gpioa";

};

such as pull-up, multi drive, etc.

Required properties for iomux controller:

- compatible: "atmel,at91rm9200-pinctrl"

- compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"

- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be

  configured in this periph mode. All the periph and bank need to be describe.

  Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.

Required properties for pin configuration node:

- fsl,pins: two integers array, represents a group of pins mux and config

  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a

  pin working on a specific function, which consists of a tuple of

  <mux_reg conf_reg input_reg mux_val input_val>.  CONFIG is the pad setting

  value like pull-up on this pin.

- fsl,pins: each entry consists of 6 integers and represents the mux and config

  setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val

  input_val> are specified using a PIN_FUNC_ID macro, which can be found in

  imx*-pinfunc.h under device tree source folder. The last integer CONFIG is

  the pad setting value like pull-up on this pin. And that's why fsl,pins entry

  looks like <PIN_FUNC_ID CONFIG> in the example below.

Bits used for CONFIG:

NO_PAD_CTL(1 << 31): indicate this pin does not need config.

	/* shared pinctrl settings */

	usdhc4 {

		pinctrl_usdhc4_1: usdhc4grp-1 {

			fsl,pins = <1386 0x17059	/* MX6Q_PAD_SD4_CMD__USDHC4_CMD */

				    1392 0x10059	/* MX6Q_PAD_SD4_CLK__USDHC4_CLK	*/

				    1462 0x17059	/* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */

				    1470 0x17059	/* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */

				    1478 0x17059	/* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */

				    1486 0x17059	/* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */

				    1493 0x17059	/* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */

				    1501 0x17059	/* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */

				    1509 0x17059	/* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */

				    1517 0x17059>;	/* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */

		};

			fsl,pins = <

				MX6QDL_PAD_SD4_CMD__SD4_CMD    0x17059

				MX6QDL_PAD_SD4_CLK__SD4_CLK    0x10059

				MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059

				MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059

				MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059

				MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059

				MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059

				MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059

				MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059

				MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059

			>;

	};

	....

};

0x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed,

80Ohm driver strength and Fast Slew Rate.

User should refer to each SoC spec to set the correct value.

TODO: when dtc macro support is available, we can change above raw data

to dt macro which can get better readability in dts file.