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Commit 89a35e51 authored by Archit Taneja's avatar Archit Taneja Committed by Tomi Valkeinen
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OMAP2PLUS: DSS2: Change enum "dss_clk_source" to "omap_dss_clk_source" 



Change enum dss_clk_source to omap_dss_clock_source and move it to
'plat/display.h'. Change the enum members to attach "OMAP_" in the beginning.
These changes are done in order to specify the clock sources for DSS in the
board file.

Signed-off-by: default avatarArchit Taneja <archit@ti.com>
Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
parent 14e4d784

drivers/video/omap2/dss/dispc.c

+6 −6
Original line number Diff line number Diff line
@@ -2356,10 +2356,10 @@ unsigned long dispc_fclk_rate(void) 
	unsigned long r = 0;



	switch (dss_get_dispc_clk_source()) {

	case DSS_CLK_SRC_FCK:

	case OMAP_DSS_CLK_SRC_FCK:

		r = dss_clk_get_rate(DSS_CLK_FCK);

		break;

	case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:

	case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:

		r = dsi_get_pll_hsdiv_dispc_rate();

		break;

	default:
@@ -2380,10 +2380,10 @@ unsigned long dispc_lclk_rate(enum omap_channel channel) 
	lcd = FLD_GET(l, 23, 16);



	switch (dss_get_lcd_clk_source(channel)) {

	case DSS_CLK_SRC_FCK:

	case OMAP_DSS_CLK_SRC_FCK:

		r = dss_clk_get_rate(DSS_CLK_FCK);

		break;

	case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:

	case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:

		r = dsi_get_pll_hsdiv_dispc_rate();

		break;

	default:
@@ -2412,8 +2412,8 @@ void dispc_dump_clocks(struct seq_file *s) 
{

	int lcd, pcd;

	u32 l;

	enum dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();

	enum dss_clk_source lcd_clk_src;

	enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();

	enum omap_dss_clk_source lcd_clk_src;



	enable_clocks(1);

drivers/video/omap2/dss/dpi.c

+2 −2
Original line number Diff line number Diff line
@@ -57,7 +57,7 @@ static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft, 
	if (r)

		return r;



	dss_select_dispc_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC);

	dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC);



	r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);

	if (r)
@@ -217,7 +217,7 @@ void omapdss_dpi_display_disable(struct omap_dss_device *dssdev) 
	dssdev->manager->disable(dssdev->manager);



#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL

	dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);

	dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);

	dsi_pll_uninit();

	dss_clk_disable(DSS_CLK_SYSCK);

#endif

drivers/video/omap2/dss/dsi.c

+19 −19
Original line number Diff line number Diff line
@@ -1009,7 +1009,7 @@ static unsigned long dsi_fclk_rate(void) 
{

	unsigned long r;



	if (dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK) {

	if (dss_get_dsi_clk_source() == OMAP_DSS_CLK_SRC_FCK) {

		/* DSI FCLK source is DSS_CLK_FCK */

		r = dss_clk_get_rate(DSS_CLK_FCK);

	} else {
@@ -1317,12 +1317,12 @@ int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo) 
	DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);



	DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,

		dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),

		dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),

		dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),

		dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),

		cinfo->dsi_pll_hsdiv_dispc_clk);

	DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,

		dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),

		dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),

		dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),

		dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),

		cinfo->dsi_pll_hsdiv_dsi_clk);



	dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, &regn_start, &regn_end);
@@ -1497,7 +1497,7 @@ void dsi_pll_uninit(void) 
void dsi_dump_clocks(struct seq_file *s)

{

	struct dsi_clock_info *cinfo = &dsi.current_cinfo;

	enum dss_clk_source dispc_clk_src, dsi_clk_src;

	enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;



	dispc_clk_src = dss_get_dispc_clk_source();

	dsi_clk_src = dss_get_dsi_clk_source();
@@ -1519,7 +1519,7 @@ void dsi_dump_clocks(struct seq_file *s) 
			dss_feat_get_clk_source_name(dispc_clk_src),

			cinfo->dsi_pll_hsdiv_dispc_clk,

			cinfo->regm_dispc,

			dispc_clk_src == DSS_CLK_SRC_FCK ?

			dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?

			"off" : "on");



	seq_printf(s,	"%s (%s)\t%-16luregm_dsi %u\t(%s)\n",
@@ -1527,7 +1527,7 @@ void dsi_dump_clocks(struct seq_file *s) 
			dss_feat_get_clk_source_name(dsi_clk_src),

			cinfo->dsi_pll_hsdiv_dsi_clk,

			cinfo->regm_dsi,

			dsi_clk_src == DSS_CLK_SRC_FCK ?

			dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?

			"off" : "on");



	seq_printf(s,	"- DSI -\n");
@@ -3455,10 +3455,10 @@ static int dsi_display_init_dsi(struct omap_dss_device *dssdev) 
	if (r)

		goto err1;



	dss_select_dispc_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC);

	dss_select_dsi_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI);

	dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC);

	dss_select_dsi_clk_source(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI);

	dss_select_lcd_clk_source(dssdev->manager->id,

		DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC);

		OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC);



	DSSDBG("PLL OK\n");
@@ -3494,8 +3494,8 @@ static int dsi_display_init_dsi(struct omap_dss_device *dssdev) 
err3:

	dsi_complexio_uninit();

err2:

	dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);

	dss_select_dsi_clk_source(DSS_CLK_SRC_FCK);

	dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);

	dss_select_dsi_clk_source(OMAP_DSS_CLK_SRC_FCK);

err1:

	dsi_pll_uninit();

err0:
@@ -3511,8 +3511,8 @@ static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev) 
	dsi_vc_enable(2, 0);

	dsi_vc_enable(3, 0);



	dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);

	dss_select_dsi_clk_source(DSS_CLK_SRC_FCK);

	dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);

	dss_select_dsi_clk_source(OMAP_DSS_CLK_SRC_FCK);

	dsi_complexio_uninit();

	dsi_pll_uninit();

}
@@ -3703,16 +3703,16 @@ void dsi_wait_pll_hsdiv_dispc_active(void) 
{

	if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1)

		DSSERR("%s (%s) not active\n",

			dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),

			dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));

			dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),

			dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));

}



void dsi_wait_pll_hsdiv_dsi_active(void)

{

	if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1)

		DSSERR("%s (%s) not active\n",

			dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),

			dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));

			dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),

			dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));

}



static void dsi_calc_clock_param_ranges(void)

drivers/video/omap2/dss/dss.c

+25 −25
Original line number Diff line number Diff line
@@ -75,17 +75,17 @@ static struct { 
	struct dss_clock_info cache_dss_cinfo;

	struct dispc_clock_info cache_dispc_cinfo;



	enum dss_clk_source dsi_clk_source;

	enum dss_clk_source dispc_clk_source;

	enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];

	enum omap_dss_clk_source dsi_clk_source;

	enum omap_dss_clk_source dispc_clk_source;

	enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];



	u32		ctx[DSS_SZ_REGS / sizeof(u32)];

} dss;



static const char * const dss_generic_clk_source_names[] = {

	[DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]	= "DSI_PLL_HSDIV_DISPC",

	[DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]		= "DSI_PLL_HSDIV_DSI",

	[DSS_CLK_SRC_FCK]			= "DSS_FCK",

	[OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]	= "DSI_PLL_HSDIV_DISPC",

	[OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]	= "DSI_PLL_HSDIV_DSI",

	[OMAP_DSS_CLK_SRC_FCK]			= "DSS_FCK",

};



static void dss_clk_enable_all_no_ctx(void);
@@ -230,7 +230,7 @@ void dss_sdi_disable(void) 
	REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */

}



const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src)

const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src)

{

	return dss_generic_clk_source_names[clk_src];

}
@@ -246,8 +246,8 @@ void dss_dump_clocks(struct seq_file *s) 


	seq_printf(s, "- DSS -\n");



	fclk_name = dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK);

	fclk_real_name = dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK);

	fclk_name = dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK);

	fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK);

	fclk_rate = dss_clk_get_rate(DSS_CLK_FCK);



	if (dss.dpll4_m4_ck) {
@@ -300,16 +300,16 @@ void dss_dump_regs(struct seq_file *s) 
#undef DUMPREG

}



void dss_select_dispc_clk_source(enum dss_clk_source clk_src)

void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src)

{

	int b;

	u8 start, end;



	switch (clk_src) {

	case DSS_CLK_SRC_FCK:

	case OMAP_DSS_CLK_SRC_FCK:

		b = 0;

		break;

	case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:

	case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:

		b = 1;

		dsi_wait_pll_hsdiv_dispc_active();

		break;
@@ -324,15 +324,15 @@ void dss_select_dispc_clk_source(enum dss_clk_source clk_src) 
	dss.dispc_clk_source = clk_src;

}



void dss_select_dsi_clk_source(enum dss_clk_source clk_src)

void dss_select_dsi_clk_source(enum omap_dss_clk_source clk_src)

{

	int b;



	switch (clk_src) {

	case DSS_CLK_SRC_FCK:

	case OMAP_DSS_CLK_SRC_FCK:

		b = 0;

		break;

	case DSS_CLK_SRC_DSI_PLL_HSDIV_DSI:

	case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI:

		b = 1;

		dsi_wait_pll_hsdiv_dsi_active();

		break;
@@ -346,7 +346,7 @@ void dss_select_dsi_clk_source(enum dss_clk_source clk_src) 
}



void dss_select_lcd_clk_source(enum omap_channel channel,

		enum dss_clk_source clk_src)

		enum omap_dss_clk_source clk_src)

{

	int b, ix, pos;
@@ -354,10 +354,10 @@ void dss_select_lcd_clk_source(enum omap_channel channel, 
		return;



	switch (clk_src) {

	case DSS_CLK_SRC_FCK:

	case OMAP_DSS_CLK_SRC_FCK:

		b = 0;

		break;

	case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:

	case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:

		BUG_ON(channel != OMAP_DSS_CHANNEL_LCD);

		b = 1;

		dsi_wait_pll_hsdiv_dispc_active();
@@ -373,17 +373,17 @@ void dss_select_lcd_clk_source(enum omap_channel channel, 
	dss.lcd_clk_source[ix] = clk_src;

}



enum dss_clk_source dss_get_dispc_clk_source(void)

enum omap_dss_clk_source dss_get_dispc_clk_source(void)

{

	return dss.dispc_clk_source;

}



enum dss_clk_source dss_get_dsi_clk_source(void)

enum omap_dss_clk_source dss_get_dsi_clk_source(void)

{

	return dss.dsi_clk_source;

}



enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)

enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)

{

	if (dss_has_feature(FEAT_LCD_CLK_SRC)) {

		int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
@@ -711,10 +711,10 @@ static int dss_init(void) 


	dss.dpll4_m4_ck = dpll4_m4_ck;



	dss.dsi_clk_source = DSS_CLK_SRC_FCK;

	dss.dispc_clk_source = DSS_CLK_SRC_FCK;

	dss.lcd_clk_source[0] = DSS_CLK_SRC_FCK;

	dss.lcd_clk_source[1] = DSS_CLK_SRC_FCK;

	dss.dsi_clk_source = OMAP_DSS_CLK_SRC_FCK;

	dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK;

	dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;

	dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;



	dss_save_context();

drivers/video/omap2/dss/dss.h

+7 −16
Original line number Diff line number Diff line
@@ -117,15 +117,6 @@ enum dss_clock { 
	DSS_CLK_VIDFCK	= 1 << 4,	/* DSS_96M_FCLK*/

};



enum dss_clk_source {

	DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,	/* OMAP3: DSI1_PLL_FCLK

						 * OMAP4: PLL1_CLK1 */

	DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,		/* OMAP3: DSI2_PLL_FCLK

						 * OMAP4: PLL1_CLK2 */

	DSS_CLK_SRC_FCK,			/* OMAP2/3: DSS1_ALWON_FCLK

						 * OMAP4: DSS_FCLK */

};



enum dss_hdmi_venc_clk_source_select {

	DSS_VENC_TV_CLK = 0,

	DSS_HDMI_M_PCLK = 1,
@@ -236,7 +227,7 @@ void dss_clk_enable(enum dss_clock clks); 
void dss_clk_disable(enum dss_clock clks);

unsigned long dss_clk_get_rate(enum dss_clock clk);

int dss_need_ctx_restore(void);

const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src);

const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);

void dss_dump_clocks(struct seq_file *s);



void dss_dump_regs(struct seq_file *s);
@@ -248,13 +239,13 @@ void dss_sdi_init(u8 datapairs); 
int dss_sdi_enable(void);

void dss_sdi_disable(void);



void dss_select_dispc_clk_source(enum dss_clk_source clk_src);

void dss_select_dsi_clk_source(enum dss_clk_source clk_src);

void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src);

void dss_select_dsi_clk_source(enum omap_dss_clk_source clk_src);

void dss_select_lcd_clk_source(enum omap_channel channel,

		enum dss_clk_source clk_src);

enum dss_clk_source dss_get_dispc_clk_source(void);

enum dss_clk_source dss_get_dsi_clk_source(void);

enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);

		enum omap_dss_clk_source clk_src);

enum omap_dss_clk_source dss_get_dispc_clk_source(void);

enum omap_dss_clk_source dss_get_dsi_clk_source(void);

enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);



void dss_set_venc_output(enum omap_dss_venc_type type);

void dss_set_dac_pwrdn_bgz(bool enable);