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Commit 897ea18d authored by Catalin Marinas's avatar Catalin Marinas Committed by Imran Khan
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arm64: cache: change ARCH_DMA_MINALIGN and L1_CACHE_SHIFT values 



This reverts commit 2f1c2747
and also sets ARM_DMA_MINALIGN to 128.
ARCH_DMA_MINALIGN is dependent on L1_CACHE_SHIFT but it should
be set to maximum *known* cache line size on ARMv8 systems to
avoid DMA coherecy issues. So setting ARM_DMA_MINALIGN to 128.

Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Change-Id: I3fcdba32d0bf574f0af7c924ae926dd47df75e07
Patch-mainline: linux-kernel @ 21/03/16, 17:14:03
Signed-off-by: default avatarImran Khan <kimran@codeaurora.org>
parent c1b67407

arch/arm64/include/asm/cache.h

+6 −6
Original line number Diff line number Diff line
@@ -18,17 +18,17 @@ 


#include <asm/cachetype.h>



#define L1_CACHE_SHIFT		7

#define L1_CACHE_SHIFT		6

#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)



/*

 * Memory returned by kmalloc() may be used for DMA, so we must make

 * sure that all such allocations are cache aligned. Otherwise,

 * unrelated code may cause parts of the buffer to be read into the

 * cache before the transfer is done, causing old data to be seen by

 * the CPU.

 * sure that all such allocations are aligned to the maximum *known*

 * cache line size on ARMv8 systems. Otherwise, unrelated code may cause

 * parts of the buffer to be read into the cache before the transfer is

 * done, causing old data to be seen by the CPU.

 */

#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES

#define ARCH_DMA_MINALIGN	(128)



#ifndef __ASSEMBLY__

arch/arm64/kernel/setup.c

+3 −3
Original line number Diff line number Diff line
@@ -246,9 +246,9 @@ static void __init setup_processor(void) 
	if (!cwg)

		pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",

			cls);

	if (L1_CACHE_BYTES < cls)

		pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",

			L1_CACHE_BYTES, cls);

	if (ARCH_DMA_MINALIGN < cls)

		pr_warn("ARCH_DMA_MINALIGN smaller than the Cache Writeback Granule (%d < %d)\n",

			ARCH_DMA_MINALIGN, cls);



	/*

	 * ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks.