Loading arch/mips/include/asm/i8259.h +3 −3 Original line number Diff line number Diff line Loading @@ -35,7 +35,7 @@ #define SLAVE_ICW4_DEFAULT 0x01 #define PIC_ICW4_AEOI 2 extern spinlock_t i8259A_lock; extern raw_spinlock_t i8259A_lock; extern int i8259A_irq_pending(unsigned int irq); extern void make_8259A_irq(unsigned int irq); Loading @@ -51,7 +51,7 @@ static inline int i8259_irq(void) { int irq; spin_lock(&i8259A_lock); raw_spin_lock(&i8259A_lock); /* Perform an interrupt acknowledge cycle on controller 1. */ outb(0x0C, PIC_MASTER_CMD); /* prepare for poll */ Loading @@ -78,7 +78,7 @@ static inline int i8259_irq(void) irq = -1; } spin_unlock(&i8259A_lock); raw_spin_unlock(&i8259A_lock); return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq; } Loading arch/mips/kernel/i8259.c +11 −11 Original line number Diff line number Diff line Loading @@ -29,7 +29,7 @@ */ static int i8259A_auto_eoi = -1; DEFINE_SPINLOCK(i8259A_lock); DEFINE_RAW_SPINLOCK(i8259A_lock); static void disable_8259A_irq(unsigned int irq); static void enable_8259A_irq(unsigned int irq); static void mask_and_ack_8259A(unsigned int irq); Loading Loading @@ -65,13 +65,13 @@ static void disable_8259A_irq(unsigned int irq) irq -= I8259A_IRQ_BASE; mask = 1 << irq; spin_lock_irqsave(&i8259A_lock, flags); raw_spin_lock_irqsave(&i8259A_lock, flags); cached_irq_mask |= mask; if (irq & 8) outb(cached_slave_mask, PIC_SLAVE_IMR); else outb(cached_master_mask, PIC_MASTER_IMR); spin_unlock_irqrestore(&i8259A_lock, flags); raw_spin_unlock_irqrestore(&i8259A_lock, flags); } static void enable_8259A_irq(unsigned int irq) Loading @@ -81,13 +81,13 @@ static void enable_8259A_irq(unsigned int irq) irq -= I8259A_IRQ_BASE; mask = ~(1 << irq); spin_lock_irqsave(&i8259A_lock, flags); raw_spin_lock_irqsave(&i8259A_lock, flags); cached_irq_mask &= mask; if (irq & 8) outb(cached_slave_mask, PIC_SLAVE_IMR); else outb(cached_master_mask, PIC_MASTER_IMR); spin_unlock_irqrestore(&i8259A_lock, flags); raw_spin_unlock_irqrestore(&i8259A_lock, flags); } int i8259A_irq_pending(unsigned int irq) Loading @@ -98,12 +98,12 @@ int i8259A_irq_pending(unsigned int irq) irq -= I8259A_IRQ_BASE; mask = 1 << irq; spin_lock_irqsave(&i8259A_lock, flags); raw_spin_lock_irqsave(&i8259A_lock, flags); if (irq < 8) ret = inb(PIC_MASTER_CMD) & mask; else ret = inb(PIC_SLAVE_CMD) & (mask >> 8); spin_unlock_irqrestore(&i8259A_lock, flags); raw_spin_unlock_irqrestore(&i8259A_lock, flags); return ret; } Loading Loading @@ -151,7 +151,7 @@ static void mask_and_ack_8259A(unsigned int irq) irq -= I8259A_IRQ_BASE; irqmask = 1 << irq; spin_lock_irqsave(&i8259A_lock, flags); raw_spin_lock_irqsave(&i8259A_lock, flags); /* * Lightweight spurious IRQ detection. We do not want * to overdo spurious IRQ handling - it's usually a sign Loading Loading @@ -183,7 +183,7 @@ handle_real_irq: outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */ } smtc_im_ack_irq(irq); spin_unlock_irqrestore(&i8259A_lock, flags); raw_spin_unlock_irqrestore(&i8259A_lock, flags); return; spurious_8259A_irq: Loading Loading @@ -264,7 +264,7 @@ static void init_8259A(int auto_eoi) i8259A_auto_eoi = auto_eoi; spin_lock_irqsave(&i8259A_lock, flags); raw_spin_lock_irqsave(&i8259A_lock, flags); outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */ outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */ Loading Loading @@ -298,7 +298,7 @@ static void init_8259A(int auto_eoi) outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */ outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */ spin_unlock_irqrestore(&i8259A_lock, flags); raw_spin_unlock_irqrestore(&i8259A_lock, flags); } /* Loading arch/mips/loongson/lemote-2f/irq.c +2 −2 Original line number Diff line number Diff line Loading @@ -38,7 +38,7 @@ int mach_i8259_irq(void) irq = -1; if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) { spin_lock(&i8259A_lock); raw_spin_lock(&i8259A_lock); isr = inb(PIC_MASTER_CMD) & ~inb(PIC_MASTER_IMR) & ~(1 << PIC_CASCADE_IR); if (!isr) Loading @@ -56,7 +56,7 @@ int mach_i8259_irq(void) if (~inb(PIC_MASTER_ISR) & 0x80) irq = -1; } spin_unlock(&i8259A_lock); raw_spin_unlock(&i8259A_lock); } return irq; Loading Loading
arch/mips/include/asm/i8259.h +3 −3 Original line number Diff line number Diff line Loading @@ -35,7 +35,7 @@ #define SLAVE_ICW4_DEFAULT 0x01 #define PIC_ICW4_AEOI 2 extern spinlock_t i8259A_lock; extern raw_spinlock_t i8259A_lock; extern int i8259A_irq_pending(unsigned int irq); extern void make_8259A_irq(unsigned int irq); Loading @@ -51,7 +51,7 @@ static inline int i8259_irq(void) { int irq; spin_lock(&i8259A_lock); raw_spin_lock(&i8259A_lock); /* Perform an interrupt acknowledge cycle on controller 1. */ outb(0x0C, PIC_MASTER_CMD); /* prepare for poll */ Loading @@ -78,7 +78,7 @@ static inline int i8259_irq(void) irq = -1; } spin_unlock(&i8259A_lock); raw_spin_unlock(&i8259A_lock); return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq; } Loading
arch/mips/kernel/i8259.c +11 −11 Original line number Diff line number Diff line Loading @@ -29,7 +29,7 @@ */ static int i8259A_auto_eoi = -1; DEFINE_SPINLOCK(i8259A_lock); DEFINE_RAW_SPINLOCK(i8259A_lock); static void disable_8259A_irq(unsigned int irq); static void enable_8259A_irq(unsigned int irq); static void mask_and_ack_8259A(unsigned int irq); Loading Loading @@ -65,13 +65,13 @@ static void disable_8259A_irq(unsigned int irq) irq -= I8259A_IRQ_BASE; mask = 1 << irq; spin_lock_irqsave(&i8259A_lock, flags); raw_spin_lock_irqsave(&i8259A_lock, flags); cached_irq_mask |= mask; if (irq & 8) outb(cached_slave_mask, PIC_SLAVE_IMR); else outb(cached_master_mask, PIC_MASTER_IMR); spin_unlock_irqrestore(&i8259A_lock, flags); raw_spin_unlock_irqrestore(&i8259A_lock, flags); } static void enable_8259A_irq(unsigned int irq) Loading @@ -81,13 +81,13 @@ static void enable_8259A_irq(unsigned int irq) irq -= I8259A_IRQ_BASE; mask = ~(1 << irq); spin_lock_irqsave(&i8259A_lock, flags); raw_spin_lock_irqsave(&i8259A_lock, flags); cached_irq_mask &= mask; if (irq & 8) outb(cached_slave_mask, PIC_SLAVE_IMR); else outb(cached_master_mask, PIC_MASTER_IMR); spin_unlock_irqrestore(&i8259A_lock, flags); raw_spin_unlock_irqrestore(&i8259A_lock, flags); } int i8259A_irq_pending(unsigned int irq) Loading @@ -98,12 +98,12 @@ int i8259A_irq_pending(unsigned int irq) irq -= I8259A_IRQ_BASE; mask = 1 << irq; spin_lock_irqsave(&i8259A_lock, flags); raw_spin_lock_irqsave(&i8259A_lock, flags); if (irq < 8) ret = inb(PIC_MASTER_CMD) & mask; else ret = inb(PIC_SLAVE_CMD) & (mask >> 8); spin_unlock_irqrestore(&i8259A_lock, flags); raw_spin_unlock_irqrestore(&i8259A_lock, flags); return ret; } Loading Loading @@ -151,7 +151,7 @@ static void mask_and_ack_8259A(unsigned int irq) irq -= I8259A_IRQ_BASE; irqmask = 1 << irq; spin_lock_irqsave(&i8259A_lock, flags); raw_spin_lock_irqsave(&i8259A_lock, flags); /* * Lightweight spurious IRQ detection. We do not want * to overdo spurious IRQ handling - it's usually a sign Loading Loading @@ -183,7 +183,7 @@ handle_real_irq: outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */ } smtc_im_ack_irq(irq); spin_unlock_irqrestore(&i8259A_lock, flags); raw_spin_unlock_irqrestore(&i8259A_lock, flags); return; spurious_8259A_irq: Loading Loading @@ -264,7 +264,7 @@ static void init_8259A(int auto_eoi) i8259A_auto_eoi = auto_eoi; spin_lock_irqsave(&i8259A_lock, flags); raw_spin_lock_irqsave(&i8259A_lock, flags); outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */ outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */ Loading Loading @@ -298,7 +298,7 @@ static void init_8259A(int auto_eoi) outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */ outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */ spin_unlock_irqrestore(&i8259A_lock, flags); raw_spin_unlock_irqrestore(&i8259A_lock, flags); } /* Loading
arch/mips/loongson/lemote-2f/irq.c +2 −2 Original line number Diff line number Diff line Loading @@ -38,7 +38,7 @@ int mach_i8259_irq(void) irq = -1; if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) { spin_lock(&i8259A_lock); raw_spin_lock(&i8259A_lock); isr = inb(PIC_MASTER_CMD) & ~inb(PIC_MASTER_IMR) & ~(1 << PIC_CASCADE_IR); if (!isr) Loading @@ -56,7 +56,7 @@ int mach_i8259_irq(void) if (~inb(PIC_MASTER_ISR) & 0x80) irq = -1; } spin_unlock(&i8259A_lock); raw_spin_unlock(&i8259A_lock); } return irq; Loading