Loading arch/arm/boot/dts/qcom/msm-arm-smmu-8996.dtsi +3 −3 Original line number Diff line number Diff line Loading @@ -162,8 +162,7 @@ qcom,skip-init; qcom,no-smr-check; #global-interrupts = <1>; interrupts = <0 353 0>, <0 348 0>, <0 349 0>, <0 350 0>, <0 351 0>; interrupts = <0 73 0>, <0 320 0>, <0 321 0>, <0 322 0>, <0 323 0>; vdd-supply = <&gdsc_mmagic_mdss>; clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>, <&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>, Loading @@ -182,7 +181,8 @@ qcom,register-save; qcom,skip-init; #global-interrupts = <1>; interrupts = <0 73 0>, <0 320 0>, <0 321 0>, <0 322 0>, <0 323 0>; interrupts = <0 353 0>, <0 348 0>, <0 349 0>, <0 350 0>, <0 351 0>; vdd-supply = <&gdsc_mmagic_mdss>; clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>, <&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>, Loading Loading
arch/arm/boot/dts/qcom/msm-arm-smmu-8996.dtsi +3 −3 Original line number Diff line number Diff line Loading @@ -162,8 +162,7 @@ qcom,skip-init; qcom,no-smr-check; #global-interrupts = <1>; interrupts = <0 353 0>, <0 348 0>, <0 349 0>, <0 350 0>, <0 351 0>; interrupts = <0 73 0>, <0 320 0>, <0 321 0>, <0 322 0>, <0 323 0>; vdd-supply = <&gdsc_mmagic_mdss>; clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>, <&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>, Loading @@ -182,7 +181,8 @@ qcom,register-save; qcom,skip-init; #global-interrupts = <1>; interrupts = <0 73 0>, <0 320 0>, <0 321 0>, <0 322 0>, <0 323 0>; interrupts = <0 353 0>, <0 348 0>, <0 349 0>, <0 350 0>, <0 351 0>; vdd-supply = <&gdsc_mmagic_mdss>; clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>, <&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>, Loading