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Commit 87d08bc9 authored by Markos Chandras's avatar Markos Chandras Committed by Ralf Baechle
Browse files

MIPS: asm: Add register definitions for Hardware Table Walker 



Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7326/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent e647e6b5

arch/mips/include/asm/mipsregs.h

+44 −0
Original line number Diff line number Diff line
@@ -706,6 +706,37 @@ 
#define MIPS_SEGCFG_MK		_ULCAST_(1)

#define MIPS_SEGCFG_UK		_ULCAST_(0)



#define MIPS_PWFIELD_GDI_SHIFT	24

#define MIPS_PWFIELD_GDI_MASK	0x3f000000

#define MIPS_PWFIELD_UDI_SHIFT	18

#define MIPS_PWFIELD_UDI_MASK	0x00fc0000

#define MIPS_PWFIELD_MDI_SHIFT	12

#define MIPS_PWFIELD_MDI_MASK	0x0003f000

#define MIPS_PWFIELD_PTI_SHIFT	6

#define MIPS_PWFIELD_PTI_MASK	0x00000fc0

#define MIPS_PWFIELD_PTEI_SHIFT	0

#define MIPS_PWFIELD_PTEI_MASK	0x0000003f



#define MIPS_PWSIZE_GDW_SHIFT	24

#define MIPS_PWSIZE_GDW_MASK	0x3f000000

#define MIPS_PWSIZE_UDW_SHIFT	18

#define MIPS_PWSIZE_UDW_MASK	0x00fc0000

#define MIPS_PWSIZE_MDW_SHIFT	12

#define MIPS_PWSIZE_MDW_MASK	0x0003f000

#define MIPS_PWSIZE_PTW_SHIFT	6

#define MIPS_PWSIZE_PTW_MASK	0x00000fc0

#define MIPS_PWSIZE_PTEW_SHIFT	0

#define MIPS_PWSIZE_PTEW_MASK	0x0000003f



#define MIPS_PWCTL_PWEN_SHIFT	31

#define MIPS_PWCTL_PWEN_MASK	0x80000000

#define MIPS_PWCTL_DPH_SHIFT	7

#define MIPS_PWCTL_DPH_MASK	0x00000080

#define MIPS_PWCTL_HUGEPG_SHIFT	6

#define MIPS_PWCTL_HUGEPG_MASK	0x00000060

#define MIPS_PWCTL_PSN_SHIFT	0

#define MIPS_PWCTL_PSN_MASK	0x0000003f



#ifndef __ASSEMBLY__



/*
@@ -1201,6 +1232,19 @@ do { \ 
#define read_c0_segctl2()	__read_32bit_c0_register($5, 4)

#define write_c0_segctl2(val)	__write_32bit_c0_register($5, 4, val)



/* Hardware Page Table Walker */

#define read_c0_pwbase()	__read_ulong_c0_register($5, 5)

#define write_c0_pwbase(val)	__write_ulong_c0_register($5, 5, val)



#define read_c0_pwfield()	__read_ulong_c0_register($5, 6)

#define write_c0_pwfield(val)	__write_ulong_c0_register($5, 6, val)



#define read_c0_pwsize()	__read_ulong_c0_register($5, 7)

#define write_c0_pwsize(val)	__write_ulong_c0_register($5, 7, val)



#define read_c0_pwctl()		__read_32bit_c0_register($6, 6)

#define write_c0_pwctl(val)	__write_32bit_c0_register($6, 6, val)



/* Cavium OCTEON (cnMIPS) */

#define read_c0_cvmcount()	__read_ulong_c0_register($9, 6)

#define write_c0_cvmcount(val)	__write_ulong_c0_register($9, 6, val)