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Commit 86d37969 authored by Hongtao Jia's avatar Hongtao Jia Committed by Scott Wood
Browse files

powerpc/mpic: Add get_version API both for internal and external use 



MPIC version is useful information for both mpic_alloc() and mpic_init().
The patch provide an API to get MPIC version for reusing the code.
Also, some other IP block may need MPIC version for their own use.
The API for external use is also provided.

Signed-off-by: default avatarJia Hongtao <hongtao.jia@freescale.com>
Signed-off-by: default avatarLi Yang <leoli@freescale.com>
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
parent 3978bdb4

arch/powerpc/include/asm/mpic.h

+3 −0
Original line number Diff line number Diff line
@@ -393,6 +393,9 @@ struct mpic 
#define	MPIC_REGSET_STANDARD		MPIC_REGSET(0)	/* Original MPIC */

#define	MPIC_REGSET_TSI108		MPIC_REGSET(1)	/* Tsi108/109 PIC */



/* Get the version of primary MPIC */

extern u32 fsl_mpic_primary_get_version(void);



/* Allocate the controller structure and setup the linux irq descs

 * for the range if interrupts passed in. No HW initialization is

 * actually performed.

arch/powerpc/sysdev/mpic.c

+25 −7
Original line number Diff line number Diff line
@@ -1173,10 +1173,33 @@ static struct irq_domain_ops mpic_host_ops = { 
	.xlate = mpic_host_xlate,

};



static u32 fsl_mpic_get_version(struct mpic *mpic)

{

	u32 brr1;



	if (!(mpic->flags & MPIC_FSL))

		return 0;



	brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,

			MPIC_FSL_BRR1);



	return brr1 & MPIC_FSL_BRR1_VER;

}



/*

 * Exported functions

 */



u32 fsl_mpic_primary_get_version(void)

{

	struct mpic *mpic = mpic_primary;



	if (mpic)

		return fsl_mpic_get_version(mpic);



	return 0;

}



struct mpic * __init mpic_alloc(struct device_node *node,

				phys_addr_t phys_addr,

				unsigned int flags,
@@ -1323,7 +1346,6 @@ struct mpic * __init mpic_alloc(struct device_node *node, 
	mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);



	if (mpic->flags & MPIC_FSL) {

		u32 brr1;

		int ret;



		/*
@@ -1334,9 +1356,7 @@ struct mpic * __init mpic_alloc(struct device_node *node, 
		mpic_map(mpic, mpic->paddr, &mpic->thiscpuregs,

			 MPIC_CPU_THISBASE, 0x1000);



		brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,

				MPIC_FSL_BRR1);

		fsl_version = brr1 & MPIC_FSL_BRR1_VER;

		fsl_version = fsl_mpic_get_version(mpic);



		/* Error interrupt mask register (EIMR) is required for

		 * handling individual device error interrupts. EIMR
@@ -1526,9 +1546,7 @@ void __init mpic_init(struct mpic *mpic) 
	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);



	if (mpic->flags & MPIC_FSL) {

		u32 brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,

				      MPIC_FSL_BRR1);

		u32 version = brr1 & MPIC_FSL_BRR1_VER;

		u32 version = fsl_mpic_get_version(mpic);



		/*

		 * Timer group B is present at the latest in MPIC 3.1 (e.g.