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Commit 85de9d17 authored by Denis Carikli's avatar Denis Carikli Committed by Russell King
Browse files

imx-drm: match ipu_di_signal_cfg's clk_pol with its description. 



According to the datasheet, setting the di0_polarity_disp_clk
field in the GENERAL di register sets the output clock polarity
to active high.

Signed-off-by: default avatarDenis Carikli <denis@eukrea.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent c9eaa447

drivers/staging/imx-drm/ipu-v3/ipu-di.c

+1 −1
Original line number Diff line number Diff line
@@ -595,7 +595,7 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig) 
		}

	}



	if (!sig->clk_pol)

	if (sig->clk_pol)

		di_gen |= DI_GEN_POLARITY_DISP_CLK;



	ipu_di_write(di, di_gen, DI_GENERAL);

drivers/staging/imx-drm/ipuv3-crtc.c

+1 −1
Original line number Diff line number Diff line
@@ -158,7 +158,7 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc, 
		sig_cfg.Vsync_pol = 1;



	sig_cfg.enable_pol = 1;

	sig_cfg.clk_pol = 1;

	sig_cfg.clk_pol = 0;

	sig_cfg.width = mode->hdisplay;

	sig_cfg.height = mode->vdisplay;

	sig_cfg.pixel_fmt = out_pixel_fmt;