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Commit 859ae233 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2013-12-13' of... 

Merge tag 'drm-intel-next-2013-12-13' of git://people.freedesktop.org/~danvet/drm-intel into drm-next

- fbc1 improvements from Ville (pre-gm45).
- vlv forcewake improvements from Deepak S.
- Some corner-cases fixes from Mika for the context hang stat code.
- pc8 improvements and prep work for runtime D3 from Paulo, almost ready for
  primetime.
- gen2 dpll fixes from Ville.
- DSI improvements from Shobhit Kumar.
- A few smaller fixes and improvements all over.

[airlied: intel_ddi.c conflict fixed up]

* tag 'drm-intel-next-2013-12-13' of git://people.freedesktop.org/~danvet/drm-intel: (61 commits)
  drm/i915/bdw: Implement ff workarounds
  drm/i915/bdw: Force all Data Cache Data Port access to be Non-Coherent
  drm/i915/bdw: Don't use forcewake needlessly
  drm/i915: Clear out old GT FIFO errors in intel_uncore_early_sanitize()
  drm/i915: dont call irq_put when irq test is on
  drm/i915: Rework the FBC interval/stall stuff a bit
  drm/i915: Enable FBC for all mobile gen2 and gen3 platforms
  drm/i915: FBC_CONTROL2 is gen4 only
  drm/i915: Gen2 FBC1 CFB pitch wants 32B units
  drm/i915: split intel_ddi_pll_mode_set in 2 pieces
  drm/i915: Fix timeout with missed interrupts in __wait_seqno
  drm/i915: touch VGA MSR after we enable the power well
  drm/i915: extract hsw_power_well_post_{enable, disable}
  drm/i915: remove i915_disable_vga_mem declaration
  drm/i915: Parametrize the dphy and other spec specific parameters
  drm/i915: Remove redundant DSI PLL enabling
  drm/i915: Reorganize the DSI enable/disable sequence
  drm/i915: Try harder to get best m, n, p values with minimal error
  drm/i915: Compute dsi_clk from pixel clock
  drm/i915: Use FLISDSI interface for band gap reset
  ...

Conflicts:
	drivers/gpu/drm/i915/intel_ddi.c
parents 785e15ec ab57fff1

drivers/gpu/drm/i915/i915_debugfs.c

+42 −3
Original line number Diff line number Diff line
@@ -564,10 +564,12 @@ static int i915_gem_seqno_info(struct seq_file *m, void *data) 
	ret = mutex_lock_interruptible(&dev->struct_mutex);

	if (ret)

		return ret;

	intel_runtime_pm_get(dev_priv);



	for_each_ring(ring, dev_priv, i)

		i915_ring_seqno_info(m, ring);



	intel_runtime_pm_put(dev_priv);

	mutex_unlock(&dev->struct_mutex);



	return 0;
@@ -585,6 +587,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data) 
	ret = mutex_lock_interruptible(&dev->struct_mutex);

	if (ret)

		return ret;

	intel_runtime_pm_get(dev_priv);



	if (INTEL_INFO(dev)->gen >= 8) {

		int i;
@@ -711,6 +714,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data) 
		}

		i915_ring_seqno_info(m, ring);

	}

	intel_runtime_pm_put(dev_priv);

	mutex_unlock(&dev->struct_mutex);



	return 0;
@@ -904,9 +908,11 @@ static int i915_rstdby_delays(struct seq_file *m, void *unused) 
	ret = mutex_lock_interruptible(&dev->struct_mutex);

	if (ret)

		return ret;

	intel_runtime_pm_get(dev_priv);



	crstanddelay = I915_READ16(CRSTANDVID);



	intel_runtime_pm_put(dev_priv);

	mutex_unlock(&dev->struct_mutex);



	seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
@@ -919,7 +925,9 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) 
	struct drm_info_node *node = (struct drm_info_node *) m->private;

	struct drm_device *dev = node->minor->dev;

	drm_i915_private_t *dev_priv = dev->dev_private;

	int ret;

	int ret = 0;



	intel_runtime_pm_get(dev_priv);



	flush_delayed_work(&dev_priv->rps.delayed_resume_work);
@@ -945,7 +953,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) 
		/* RPSTAT1 is in the GT power well */

		ret = mutex_lock_interruptible(&dev->struct_mutex);

		if (ret)

			return ret;

			goto out;



		gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
@@ -1033,7 +1041,9 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) 
		seq_puts(m, "no P-state info available\n");

	}



	return 0;

out:

	intel_runtime_pm_put(dev_priv);

	return ret;

}



static int i915_delayfreq_table(struct seq_file *m, void *unused)
@@ -1047,6 +1057,7 @@ static int i915_delayfreq_table(struct seq_file *m, void *unused) 
	ret = mutex_lock_interruptible(&dev->struct_mutex);

	if (ret)

		return ret;

	intel_runtime_pm_get(dev_priv);



	for (i = 0; i < 16; i++) {

		delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
@@ -1054,6 +1065,8 @@ static int i915_delayfreq_table(struct seq_file *m, void *unused) 
			   (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);

	}



	intel_runtime_pm_put(dev_priv);



	mutex_unlock(&dev->struct_mutex);



	return 0;
@@ -1075,12 +1088,14 @@ static int i915_inttoext_table(struct seq_file *m, void *unused) 
	ret = mutex_lock_interruptible(&dev->struct_mutex);

	if (ret)

		return ret;

	intel_runtime_pm_get(dev_priv);



	for (i = 1; i <= 32; i++) {

		inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);

		seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);

	}



	intel_runtime_pm_put(dev_priv);

	mutex_unlock(&dev->struct_mutex);



	return 0;
@@ -1098,11 +1113,13 @@ static int ironlake_drpc_info(struct seq_file *m) 
	ret = mutex_lock_interruptible(&dev->struct_mutex);

	if (ret)

		return ret;

	intel_runtime_pm_get(dev_priv);



	rgvmodectl = I915_READ(MEMMODECTL);

	rstdbyctl = I915_READ(RSTDBYCTL);

	crstandvid = I915_READ16(CRSTANDVID);



	intel_runtime_pm_put(dev_priv);

	mutex_unlock(&dev->struct_mutex);



	seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
@@ -1166,6 +1183,7 @@ static int gen6_drpc_info(struct seq_file *m) 
	ret = mutex_lock_interruptible(&dev->struct_mutex);

	if (ret)

		return ret;

	intel_runtime_pm_get(dev_priv);



	spin_lock_irq(&dev_priv->uncore.lock);

	forcewake_count = dev_priv->uncore.forcewake_count;
@@ -1191,6 +1209,8 @@ static int gen6_drpc_info(struct seq_file *m) 
	sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);

	mutex_unlock(&dev_priv->rps.hw_lock);



	intel_runtime_pm_put(dev_priv);



	seq_printf(m, "Video Turbo Mode: %s\n",

		   yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));

	seq_printf(m, "HW control enabled: %s\n",
@@ -1405,6 +1425,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) 
	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);

	if (ret)

		return ret;

	intel_runtime_pm_get(dev_priv);



	seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
@@ -1421,6 +1442,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) 
			   ((ia_freq >> 8) & 0xff) * 100);

	}



	intel_runtime_pm_put(dev_priv);

	mutex_unlock(&dev_priv->rps.hw_lock);



	return 0;
@@ -1436,8 +1458,10 @@ static int i915_gfxec(struct seq_file *m, void *unused) 
	ret = mutex_lock_interruptible(&dev->struct_mutex);

	if (ret)

		return ret;

	intel_runtime_pm_get(dev_priv);



	seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));

	intel_runtime_pm_put(dev_priv);



	mutex_unlock(&dev->struct_mutex);
@@ -1617,6 +1641,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) 
	ret = mutex_lock_interruptible(&dev->struct_mutex);

	if (ret)

		return ret;

	intel_runtime_pm_get(dev_priv);



	seq_printf(m, "bit6 swizzle for X-tiling = %s\n",

		   swizzle_string(dev_priv->mm.bit_6_swizzle_x));
@@ -1648,6 +1673,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) 
		seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",

			   I915_READ(DISP_ARB_CTL));

	}

	intel_runtime_pm_put(dev_priv);

	mutex_unlock(&dev->struct_mutex);



	return 0;
@@ -1708,16 +1734,19 @@ static int i915_ppgtt_info(struct seq_file *m, void *data) 
{

	struct drm_info_node *node = (struct drm_info_node *) m->private;

	struct drm_device *dev = node->minor->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;



	int ret = mutex_lock_interruptible(&dev->struct_mutex);

	if (ret)

		return ret;

	intel_runtime_pm_get(dev_priv);



	if (INTEL_INFO(dev)->gen >= 8)

		gen8_ppgtt_info(m, dev);

	else if (INTEL_INFO(dev)->gen >= 6)

		gen6_ppgtt_info(m, dev);



	intel_runtime_pm_put(dev_priv);

	mutex_unlock(&dev->struct_mutex);



	return 0;
@@ -1791,6 +1820,8 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) 
	u32 psrperf = 0;

	bool enabled = false;



	intel_runtime_pm_get(dev_priv);



	seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));

	seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
@@ -1803,6 +1834,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) 
			EDP_PSR_PERF_CNT_MASK;

	seq_printf(m, "Performance_Counter: %u\n", psrperf);



	intel_runtime_pm_put(dev_priv);

	return 0;

}
@@ -3016,8 +3048,11 @@ i915_cache_sharing_get(void *data, u64 *val) 
	ret = mutex_lock_interruptible(&dev->struct_mutex);

	if (ret)

		return ret;

	intel_runtime_pm_get(dev_priv);



	snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);



	intel_runtime_pm_put(dev_priv);

	mutex_unlock(&dev_priv->dev->struct_mutex);



	*val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
@@ -3038,6 +3073,7 @@ i915_cache_sharing_set(void *data, u64 val) 
	if (val > 3)

		return -EINVAL;



	intel_runtime_pm_get(dev_priv);

	DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);



	/* Update the cache sharing policy here as well */
@@ -3046,6 +3082,7 @@ i915_cache_sharing_set(void *data, u64 val) 
	snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);

	I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);



	intel_runtime_pm_put(dev_priv);

	return 0;

}
@@ -3061,6 +3098,7 @@ static int i915_forcewake_open(struct inode *inode, struct file *file) 
	if (INTEL_INFO(dev)->gen < 6)

		return 0;



	intel_runtime_pm_get(dev_priv);

	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);



	return 0;
@@ -3075,6 +3113,7 @@ static int i915_forcewake_release(struct inode *inode, struct file *file) 
		return 0;



	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);

	intel_runtime_pm_put(dev_priv);



	return 0;

}

drivers/gpu/drm/i915/i915_dma.c

+12 −4
Original line number Diff line number Diff line
@@ -42,6 +42,8 @@ 
#include <linux/vga_switcheroo.h>

#include <linux/slab.h>

#include <acpi/video.h>

#include <linux/pm.h>

#include <linux/pm_runtime.h>



#define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
@@ -1667,6 +1669,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
	if (IS_GEN5(dev))

		intel_gpu_ips_init(dev_priv);



	intel_init_runtime_pm(dev_priv);



	return 0;



out_power_well:
@@ -1706,6 +1710,14 @@ int i915_driver_unload(struct drm_device *dev) 
	struct drm_i915_private *dev_priv = dev->dev_private;

	int ret;



	ret = i915_gem_suspend(dev);

	if (ret) {

		DRM_ERROR("failed to idle hardware: %d\n", ret);

		return ret;

	}



	intel_fini_runtime_pm(dev_priv);



	intel_gpu_ips_teardown();



	/* The i915.ko module is still not prepared to be loaded when
@@ -1719,10 +1731,6 @@ int i915_driver_unload(struct drm_device *dev) 
	if (dev_priv->mm.inactive_shrinker.scan_objects)

		unregister_shrinker(&dev_priv->mm.inactive_shrinker);



	ret = i915_gem_suspend(dev);

	if (ret)

		DRM_ERROR("failed to idle hardware: %d\n", ret);



	io_mapping_free(dev_priv->gtt.mappable);

	arch_phys_wc_del(dev_priv->gtt.mtrr);

drivers/gpu/drm/i915/i915_drv.c

+41 −0
Original line number Diff line number Diff line
@@ -172,6 +172,7 @@ static const struct intel_device_info intel_i85x_info = { 
	.gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,

	.cursor_needs_physical = 1,

	.has_overlay = 1, .overlay_needs_physical = 1,

	.has_fbc = 1,

	.ring_mask = RENDER_RING,

};
@@ -191,6 +192,7 @@ static const struct intel_device_info intel_i915gm_info = { 
	.cursor_needs_physical = 1,

	.has_overlay = 1, .overlay_needs_physical = 1,

	.supports_tv = 1,

	.has_fbc = 1,

	.ring_mask = RENDER_RING,

};

static const struct intel_device_info intel_i945g_info = {
@@ -203,6 +205,7 @@ static const struct intel_device_info intel_i945gm_info = { 
	.has_hotplug = 1, .cursor_needs_physical = 1,

	.has_overlay = 1, .overlay_needs_physical = 1,

	.supports_tv = 1,

	.has_fbc = 1,

	.ring_mask = RENDER_RING,

};
@@ -502,6 +505,8 @@ static int i915_drm_freeze(struct drm_device *dev) 
	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_crtc *crtc;



	intel_runtime_pm_get(dev_priv);



	/* ignore lid events during suspend */

	mutex_lock(&dev_priv->modeset_restore_lock);

	dev_priv->modeset_restore = MODESET_SUSPENDED;
@@ -688,6 +693,8 @@ static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings) 
	mutex_lock(&dev_priv->modeset_restore_lock);

	dev_priv->modeset_restore = MODESET_DONE;

	mutex_unlock(&dev_priv->modeset_restore_lock);



	intel_runtime_pm_put(dev_priv);

	return error;

}
@@ -902,6 +909,38 @@ static int i915_pm_poweroff(struct device *dev) 
	return i915_drm_freeze(drm_dev);

}



static int i915_runtime_suspend(struct device *device)

{

	struct pci_dev *pdev = to_pci_dev(device);

	struct drm_device *dev = pci_get_drvdata(pdev);

	struct drm_i915_private *dev_priv = dev->dev_private;



	WARN_ON(!HAS_RUNTIME_PM(dev));



	DRM_DEBUG_KMS("Suspending device\n");



	dev_priv->pm.suspended = true;

	intel_opregion_notify_adapter(dev, PCI_D3cold);



	return 0;

}



static int i915_runtime_resume(struct device *device)

{

	struct pci_dev *pdev = to_pci_dev(device);

	struct drm_device *dev = pci_get_drvdata(pdev);

	struct drm_i915_private *dev_priv = dev->dev_private;



	WARN_ON(!HAS_RUNTIME_PM(dev));



	DRM_DEBUG_KMS("Resuming device\n");



	intel_opregion_notify_adapter(dev, PCI_D0);

	dev_priv->pm.suspended = false;



	return 0;

}



static const struct dev_pm_ops i915_pm_ops = {

	.suspend = i915_pm_suspend,

	.resume = i915_pm_resume,
@@ -909,6 +948,8 @@ static const struct dev_pm_ops i915_pm_ops = { 
	.thaw = i915_pm_thaw,

	.poweroff = i915_pm_poweroff,

	.restore = i915_pm_resume,

	.runtime_suspend = i915_runtime_suspend,

	.runtime_resume = i915_runtime_resume,

};



static const struct vm_operations_struct i915_gem_vm_ops = {

drivers/gpu/drm/i915/i915_drv.h

+11 −3
Original line number Diff line number Diff line
@@ -323,7 +323,7 @@ struct drm_i915_error_state { 
	u32 instps[I915_NUM_RINGS];

	u32 extra_instdone[I915_NUM_INSTDONE_REG];

	u32 seqno[I915_NUM_RINGS];

	u64 bbaddr;

	u64 bbaddr[I915_NUM_RINGS];

	u32 fault_reg[I915_NUM_RINGS];

	u32 done_reg;

	u32 faddr[I915_NUM_RINGS];
@@ -372,7 +372,7 @@ struct dpll; 


struct drm_i915_display_funcs {

	bool (*fbc_enabled)(struct drm_device *dev);

	void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);

	void (*enable_fbc)(struct drm_crtc *crtc);

	void (*disable_fbc)(struct drm_device *dev);

	int (*get_display_clock_speed)(struct drm_device *dev);

	int (*get_fifo_size)(struct drm_device *dev, int plane);
@@ -695,7 +695,6 @@ struct i915_fbc { 
		struct delayed_work work;

		struct drm_crtc *crtc;

		struct drm_framebuffer *fb;

		int interval;

	} *fbc_work;



	enum no_fbc_reason {
@@ -1289,6 +1288,10 @@ struct i915_package_c8 { 
	} regsave;

};



struct i915_runtime_pm {

	bool suspended;

};



enum intel_pipe_crc_source {

	INTEL_PIPE_CRC_SOURCE_NONE,

	INTEL_PIPE_CRC_SOURCE_PLANE1,
@@ -1519,6 +1522,8 @@ typedef struct drm_i915_private { 


	struct i915_package_c8 pc8;



	struct i915_runtime_pm pm;



	/* Old dri1 support infrastructure, beware the dragons ya fools entering

	 * here! */

	struct i915_dri1_state dri1;
@@ -1843,6 +1848,7 @@ struct drm_i915_file_private { 
#define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)

#define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev))

#define HAS_PC8(dev)		(IS_HASWELL(dev)) /* XXX HSW:ULX */

#define HAS_RUNTIME_PM(dev)	false



#define INTEL_PCH_DEVICE_ID_MASK		0xff00

#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
@@ -2468,6 +2474,8 @@ u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, 
		   enum intel_sbi_destination destination);

void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,

		     enum intel_sbi_destination destination);

u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);

void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);



int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);

int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);

drivers/gpu/drm/i915/i915_gem.c

+38 −19
Original line number Diff line number Diff line
@@ -1015,9 +1015,11 @@ static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, 
			struct drm_i915_file_private *file_priv)

{

	drm_i915_private_t *dev_priv = ring->dev->dev_private;

	const bool irq_test_in_progress =

		ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);

	struct timespec before, now;

	DEFINE_WAIT(wait);

	long timeout_jiffies;

	unsigned long timeout_expire;

	int ret;



	WARN(dev_priv->pc8.irqs_disabled, "IRQs disabled\n");
@@ -1025,7 +1027,7 @@ static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, 
	if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))

		return 0;



	timeout_jiffies = timeout ? timespec_to_jiffies_timeout(timeout) : 1;

	timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0;



	if (dev_priv->info->gen >= 6 && can_wait_boost(file_priv)) {

		gen6_rps_boost(dev_priv);
@@ -1035,8 +1037,7 @@ static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, 
					 msecs_to_jiffies(100));

	}



	if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)) &&

	    WARN_ON(!ring->irq_get(ring)))

	if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))

		return -ENODEV;



	/* Record current time in case interrupted by signal, or wedged */
@@ -1044,7 +1045,6 @@ static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, 
	getrawmonotonic(&before);

	for (;;) {

		struct timer_list timer;

		unsigned long expire;



		prepare_to_wait(&ring->irq_queue, &wait,

				interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
@@ -1070,23 +1070,22 @@ static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, 
			break;

		}



		if (timeout_jiffies <= 0) {

		if (timeout && time_after_eq(jiffies, timeout_expire)) {

			ret = -ETIME;

			break;

		}



		timer.function = NULL;

		if (timeout || missed_irq(dev_priv, ring)) {

			unsigned long expire;



			setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);

			expire = jiffies + (missed_irq(dev_priv, ring) ? 1: timeout_jiffies);

			expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;

			mod_timer(&timer, expire);

		}



		io_schedule();



		if (timeout)

			timeout_jiffies = expire - jiffies;



		if (timer.function) {

			del_singleshot_timer_sync(&timer);

			destroy_timer_on_stack(&timer);
@@ -1095,6 +1094,7 @@ static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, 
	getrawmonotonic(&now);

	trace_i915_gem_request_wait_end(ring, seqno);



	if (!irq_test_in_progress)

		ring->irq_put(ring);



	finish_wait(&ring->irq_queue, &wait);
@@ -1380,6 +1380,8 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) 
	int ret = 0;

	bool write = !!(vmf->flags & FAULT_FLAG_WRITE);



	intel_runtime_pm_get(dev_priv);



	/* We don't use vmf->pgoff since that has the fake offset */

	page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>

		PAGE_SHIFT;
@@ -1427,8 +1429,10 @@ out: 
		/* If this -EIO is due to a gpu hang, give the reset code a

		 * chance to clean up the mess. Otherwise return the proper

		 * SIGBUS. */

		if (i915_terminally_wedged(&dev_priv->gpu_error))

			return VM_FAULT_SIGBUS;

		if (i915_terminally_wedged(&dev_priv->gpu_error)) {

			ret = VM_FAULT_SIGBUS;

			break;

		}

	case -EAGAIN:

		/*

		 * EAGAIN means the gpu is hung and we'll wait for the error
@@ -1443,15 +1447,22 @@ out: 
		 * EBUSY is ok: this just means that another thread

		 * already did the job.

		 */

		return VM_FAULT_NOPAGE;

		ret = VM_FAULT_NOPAGE;

		break;

	case -ENOMEM:

		return VM_FAULT_OOM;

		ret = VM_FAULT_OOM;

		break;

	case -ENOSPC:

		return VM_FAULT_SIGBUS;

		ret = VM_FAULT_SIGBUS;

		break;

	default:

		WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);

		return VM_FAULT_SIGBUS;

		ret = VM_FAULT_SIGBUS;

		break;

	}



	intel_runtime_pm_put(dev_priv);

	return ret;

}



/**
@@ -2746,7 +2757,6 @@ int i915_vma_unbind(struct i915_vma *vma) 
		obj->has_aliasing_ppgtt_mapping = 0;

	}

	i915_gem_gtt_finish_object(obj);

	i915_gem_object_unpin_pages(obj);



	list_del(&vma->mm_list);

	/* Avoid an unnecessary call to unbind on rebind. */
@@ -2754,7 +2764,6 @@ int i915_vma_unbind(struct i915_vma *vma) 
		obj->map_and_fenceable = true;



	drm_mm_remove_node(&vma->node);



	i915_gem_vma_destroy(vma);



	/* Since the unbound list is global, only move to that list if
@@ -2762,6 +2771,12 @@ int i915_vma_unbind(struct i915_vma *vma) 
	if (list_empty(&obj->vma_list))

		list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);



	/* And finally now the object is completely decoupled from this vma,

	 * we can drop its hold on the backing storage and allow it to be

	 * reaped by the shrinker.

	 */

	i915_gem_object_unpin_pages(obj);



	return 0;

}
@@ -4165,6 +4180,8 @@ void i915_gem_free_object(struct drm_gem_object *gem_obj) 
	drm_i915_private_t *dev_priv = dev->dev_private;

	struct i915_vma *vma, *next;



	intel_runtime_pm_get(dev_priv);



	trace_i915_gem_object_destroy(obj);



	if (obj->phys_obj)
@@ -4209,6 +4226,8 @@ void i915_gem_free_object(struct drm_gem_object *gem_obj) 


	kfree(obj->bit_17);

	i915_gem_object_free(obj);



	intel_runtime_pm_put(dev_priv);

}



struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,