Loading drivers/net/ethernet/qualcomm/emac/emac_hw.h +1 −0 Original line number Diff line number Diff line Loading @@ -109,6 +109,7 @@ bool emac_hw_read_tx_tstamp(struct emac_hw *hw, struct emac_hwtxtstamp *ts); #define DMAW_DLY_CNT_DEF 4 #define MDIO_CLK_25_8 3 #define MDIO_CLK_25_10 4 #define MDIO_CLK_25_28 7 #define RXQ0_RSS_HSTYP_IPV6_TCP_EN 0x20 Loading drivers/net/ethernet/qualcomm/emac/emac_phy.c +2 −2 Original line number Diff line number Diff line Loading @@ -100,7 +100,7 @@ static int emac_mdio_read(struct mii_bus *bus, int addr, int regnum) reg = reg & ~(MDIO_REG_ADDR_BMSK | MDIO_CLK_SEL_BMSK | MDIO_MODE | MDIO_PR); reg = SUP_PREAMBLE | ((MDIO_CLK_25_8 << MDIO_CLK_SEL_SHFT) & MDIO_CLK_SEL_BMSK) | ((MDIO_CLK_25_10 << MDIO_CLK_SEL_SHFT) & MDIO_CLK_SEL_BMSK) | ((regnum << MDIO_REG_ADDR_SHFT) & MDIO_REG_ADDR_BMSK) | MDIO_START | MDIO_RD_NWR; Loading Loading @@ -156,7 +156,7 @@ static int emac_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val) reg = reg & ~(MDIO_REG_ADDR_BMSK | MDIO_CLK_SEL_BMSK | MDIO_DATA_BMSK | MDIO_MODE | MDIO_PR); reg = SUP_PREAMBLE | ((MDIO_CLK_25_8 << MDIO_CLK_SEL_SHFT) & MDIO_CLK_SEL_BMSK) | ((MDIO_CLK_25_10 << MDIO_CLK_SEL_SHFT) & MDIO_CLK_SEL_BMSK) | ((regnum << MDIO_REG_ADDR_SHFT) & MDIO_REG_ADDR_BMSK) | ((val << MDIO_DATA_SHFT) & MDIO_DATA_BMSK) | MDIO_START; Loading Loading
drivers/net/ethernet/qualcomm/emac/emac_hw.h +1 −0 Original line number Diff line number Diff line Loading @@ -109,6 +109,7 @@ bool emac_hw_read_tx_tstamp(struct emac_hw *hw, struct emac_hwtxtstamp *ts); #define DMAW_DLY_CNT_DEF 4 #define MDIO_CLK_25_8 3 #define MDIO_CLK_25_10 4 #define MDIO_CLK_25_28 7 #define RXQ0_RSS_HSTYP_IPV6_TCP_EN 0x20 Loading
drivers/net/ethernet/qualcomm/emac/emac_phy.c +2 −2 Original line number Diff line number Diff line Loading @@ -100,7 +100,7 @@ static int emac_mdio_read(struct mii_bus *bus, int addr, int regnum) reg = reg & ~(MDIO_REG_ADDR_BMSK | MDIO_CLK_SEL_BMSK | MDIO_MODE | MDIO_PR); reg = SUP_PREAMBLE | ((MDIO_CLK_25_8 << MDIO_CLK_SEL_SHFT) & MDIO_CLK_SEL_BMSK) | ((MDIO_CLK_25_10 << MDIO_CLK_SEL_SHFT) & MDIO_CLK_SEL_BMSK) | ((regnum << MDIO_REG_ADDR_SHFT) & MDIO_REG_ADDR_BMSK) | MDIO_START | MDIO_RD_NWR; Loading Loading @@ -156,7 +156,7 @@ static int emac_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val) reg = reg & ~(MDIO_REG_ADDR_BMSK | MDIO_CLK_SEL_BMSK | MDIO_DATA_BMSK | MDIO_MODE | MDIO_PR); reg = SUP_PREAMBLE | ((MDIO_CLK_25_8 << MDIO_CLK_SEL_SHFT) & MDIO_CLK_SEL_BMSK) | ((MDIO_CLK_25_10 << MDIO_CLK_SEL_SHFT) & MDIO_CLK_SEL_BMSK) | ((regnum << MDIO_REG_ADDR_SHFT) & MDIO_REG_ADDR_BMSK) | ((val << MDIO_DATA_SHFT) & MDIO_DATA_BMSK) | MDIO_START; Loading