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Commit 855357a2 authored by Robert Richter's avatar Robert Richter Committed by Ingo Molnar
Browse files

perf, x86: Fix AMD family 15h FPU event constraints 



Depending on the unit mask settings some FPU events may be scheduled
only on cpu counter #3. This patch fixes this.

Signed-off-by: default avatarRobert Richter <robert.richter@amd.com>
Signed-off-by: default avatarPeter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Stephane Eranian <eranian@googlemail.com>
Link: http://lkml.kernel.org/r/1302913676-14352-3-git-send-email-robert.richter@amd.com


Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 83112e68

arch/x86/kernel/cpu/perf_event_amd.c

+17 −3
Original line number Original line Diff line number Diff line
@@ -427,7 +427,9 @@ static __initconst const struct x86_pmu amd_pmu = { 
 *

 *

 * Exceptions:

 * Exceptions:

 *

 *

 * 0x000	FP	PERF_CTL[3], PERF_CTL[5:3] (*)

 * 0x003	FP	PERF_CTL[3]

 * 0x003	FP	PERF_CTL[3]

 * 0x004	FP	PERF_CTL[3], PERF_CTL[5:3] (*)

 * 0x00B	FP	PERF_CTL[3]

 * 0x00B	FP	PERF_CTL[3]

 * 0x00D	FP	PERF_CTL[3]

 * 0x00D	FP	PERF_CTL[3]

 * 0x023	DE	PERF_CTL[2:0]

 * 0x023	DE	PERF_CTL[2:0]
@@ -448,6 +450,8 @@ static __initconst const struct x86_pmu amd_pmu = { 
 * 0x0DF	LS	PERF_CTL[5:0]

 * 0x0DF	LS	PERF_CTL[5:0]

 * 0x1D6	EX	PERF_CTL[5:0]

 * 0x1D6	EX	PERF_CTL[5:0]

 * 0x1D8	EX	PERF_CTL[5:0]

 * 0x1D8	EX	PERF_CTL[5:0]

 *

 * (*) depending on the umask all FPU counters may be used

 */

 */





static struct event_constraint amd_f15_PMC0  = EVENT_CONSTRAINT(0, 0x01, 0);

static struct event_constraint amd_f15_PMC0  = EVENT_CONSTRAINT(0, 0x01, 0);
@@ -460,18 +464,28 @@ static struct event_constraint amd_f15_PMC53 = EVENT_CONSTRAINT(0, 0x38, 0); 
static struct event_constraint *

static struct event_constraint *

amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *event)

amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *event)

{

{

	unsigned int event_code = amd_get_event_code(&event->hw);

	struct hw_perf_event *hwc = &event->hw;

	unsigned int event_code = amd_get_event_code(hwc);





	switch (event_code & AMD_EVENT_TYPE_MASK) {

	switch (event_code & AMD_EVENT_TYPE_MASK) {

	case AMD_EVENT_FP:

	case AMD_EVENT_FP:

		switch (event_code) {

		switch (event_code) {

		case 0x000:

			if (!(hwc->config & 0x0000F000ULL))

				break;

			if (!(hwc->config & 0x00000F00ULL))

				break;

			return &amd_f15_PMC3;

		case 0x004:

			if (hweight_long(hwc->config & ARCH_PERFMON_EVENTSEL_UMASK) <= 1)

				break;

			return &amd_f15_PMC3;

		case 0x003:

		case 0x003:

		case 0x00B:

		case 0x00B:

		case 0x00D:

		case 0x00D:

			return &amd_f15_PMC3;

			return &amd_f15_PMC3;

		default:

			return &amd_f15_PMC53;

		}

		}

		return &amd_f15_PMC53;

	case AMD_EVENT_LS:

	case AMD_EVENT_LS:

	case AMD_EVENT_DC:

	case AMD_EVENT_DC:

	case AMD_EVENT_EX_LS:

	case AMD_EVENT_EX_LS: