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Commit 84491c0f authored by Tim Kryger's avatar Tim Kryger Committed by Olof Johansson
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ARM: dts: bcm: Add missing UARTs for bcm11351 (bcm281xx) 



This adds in three more UARTs that were not declared earlier.

Signed-off-by: default avatarTim Kryger <tim.kryger@linaro.org>
Reviewed-by: default avatarMarkus Mayer <markus.mayer@linaro.org>
Reviewed-by: default avatarMatt Porter <matt.porter@linaro.org>
Signed-off-by: default avatarChristian Daudt <bcm@fixthebug.org>
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parent 71469fe8

arch/arm/boot/dts/bcm11351.dtsi

+30 −0
Original line number Diff line number Diff line
@@ -49,6 +49,36 @@ 
		reg-io-width = <4>;

	};



	uart@3e001000 {

		compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";

		status = "disabled";

		reg = <0x3e001000 0x1000>;

		clock-frequency = <13000000>;

		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;

		reg-shift = <2>;

		reg-io-width = <4>;

	};



	uart@3e002000 {

		compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";

		status = "disabled";

		reg = <0x3e002000 0x1000>;

		clock-frequency = <13000000>;

		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;

		reg-shift = <2>;

		reg-io-width = <4>;

	};



	uart@3e003000 {

		compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";

		status = "disabled";

		reg = <0x3e003000 0x1000>;

		clock-frequency = <13000000>;

		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;

		reg-shift = <2>;

		reg-io-width = <4>;

	};



	L2: l2-cache {

		compatible = "brcm,bcm11351-a2-pl310-cache";

		reg = <0x3ff20000 0x1000>;