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Commit 84426ce4 authored by Ghanim Fodi's avatar Ghanim Fodi Committed by Gidon Studinski
Browse files

msm: ipa3: Update registers configurations for IPAv3.5/3.5.1 



IPA v3.5 and v3.5.1 introduces changes to several IPA registers.
Some registers have new fields, some fields are shifted and
others are removed.
This change updates IPAHAL to support these changes.

CRs-fixed: 1055677
Change-Id: I2046318ba40beca75bdc2f40554fc9a458da5581
Signed-off-by: default avatarGhanim Fodi <gfodi@codeaurora.org>
Signed-off-by: default avatarGidon Studinski <gidons@codeaurora.org>
parent 4e81a4f5

drivers/platform/msm/ipa/ipa_v3/ipa_debugfs.c

+1 −1
Original line number Diff line number Diff line
@@ -1353,7 +1353,7 @@ static ssize_t ipa3_write_dbg_cnt(struct file *file, const char __user *buf, 
	memset(&dbg_cnt_ctrl, 0, sizeof(dbg_cnt_ctrl));

	dbg_cnt_ctrl.type = DBG_CNT_TYPE_GENERAL;

	dbg_cnt_ctrl.product = true;

	dbg_cnt_ctrl.src_pipe = 0x1f;

	dbg_cnt_ctrl.src_pipe = 0xff;

	dbg_cnt_ctrl.rule_idx_pipe_rule = false;

	dbg_cnt_ctrl.rule_idx = 0;

	if (option == 1)

drivers/platform/msm/ipa/ipa_v3/ipa_interrupts.c

+2 −2
Original line number Diff line number Diff line
@@ -46,7 +46,7 @@ static int ipa3_irq_mapping[IPA_IRQ_MAX] = { 
	[IPA_UC_TX_CMD_Q_NOT_FULL_IRQ]		= -1,

	[IPA_UC_TO_PROC_ACK_Q_NOT_FULL_IRQ]	= -1,

	[IPA_BAD_SNOC_ACCESS_IRQ]		= 0,

	[IPA_EOT_COAL_IRQ]			= 1,

	[IPA_EOT_COAL_IRQ]			= -1,

	[IPA_UC_IRQ_0]				= 2,

	[IPA_UC_IRQ_1]				= 3,

	[IPA_UC_IRQ_2]				= 4,
@@ -61,7 +61,7 @@ static int ipa3_irq_mapping[IPA_IRQ_MAX] = { 
	[IPA_PROC_ERR_IRQ]			= 13,

	[IPA_TX_SUSPEND_IRQ]			= 14,

	[IPA_TX_HOLB_DROP_IRQ]			= 15,

	[IPA_BAM_IDLE_IRQ]			= 16,

	[IPA_BAM_GSI_IDLE_IRQ]			= 16,

};



static void ipa3_interrupt_defer(struct work_struct *work);

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c

+161 −18
Original line number Diff line number Diff line
@@ -53,7 +53,6 @@ static const char *ipareg_name_to_str[IPA_REG_MAX] = { 
	__stringify(IPA_IRQ_EE_UC_n),

	__stringify(IPA_ENDP_INIT_HDR_METADATA_MASK_n),

	__stringify(IPA_ENDP_INIT_HDR_METADATA_n),

	__stringify(IPA_ENABLE_GSI),

	__stringify(IPA_ENDP_INIT_RSRC_GRP_n),

	__stringify(IPA_SHARED_MEM_SIZE),

	__stringify(IPA_SRAM_DIRECT_ACCESS_n),
@@ -80,6 +79,7 @@ static const char *ipareg_name_to_str[IPA_REG_MAX] = { 
	__stringify(IPA_RX_HPS_CLIENTS_MAX_DEPTH_1),

	__stringify(IPA_QSB_MAX_WRITES),

	__stringify(IPA_QSB_MAX_READS),

	__stringify(IPA_TX_CFG),

};



static void ipareg_construct_dummy(enum ipahal_reg_name reg,
@@ -136,6 +136,29 @@ static void ipareg_construct_rx_hps_clients_depth0( 
		IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_BMSK(3));

}



static void ipareg_construct_rx_hps_clients_depth0_v3_5(

	enum ipahal_reg_name reg, const void *fields, u32 *val)

{

	struct ipahal_reg_rx_hps_clients *clients =

		(struct ipahal_reg_rx_hps_clients *)fields;



	IPA_SETFIELD_IN_REG(*val, clients->client_minmax[0],

		IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_SHFT(0),

		IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_BMSK_V3_5(0));



	IPA_SETFIELD_IN_REG(*val, clients->client_minmax[1],

		IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_SHFT(1),

		IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_BMSK_V3_5(1));



	IPA_SETFIELD_IN_REG(*val, clients->client_minmax[2],

		IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_SHFT(2),

		IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_BMSK_V3_5(2));



	IPA_SETFIELD_IN_REG(*val, clients->client_minmax[3],

		IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_SHFT(3),

		IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_BMSK_V3_5(3));

}



static void ipareg_construct_rsrg_grp_xy(

	enum ipahal_reg_name reg, const void *fields, u32 *val)

{
@@ -156,6 +179,31 @@ static void ipareg_construct_rsrg_grp_xy( 
		IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_BMSK);

}



static void ipareg_construct_rsrg_grp_xy_v3_5(

	enum ipahal_reg_name reg, const void *fields, u32 *val)

{

	struct ipahal_reg_rsrc_grp_cfg *grp =

		(struct ipahal_reg_rsrc_grp_cfg *)fields;



	IPA_SETFIELD_IN_REG(*val, grp->x_min,

		IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_SHFT_V3_5,

		IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_BMSK_V3_5);

	IPA_SETFIELD_IN_REG(*val, grp->x_max,

		IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MAX_LIM_SHFT_V3_5,

		IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MAX_LIM_BMSK_V3_5);



	/* DST_23 register has only X fields at ipa V3_5 */

	if (reg == IPA_DST_RSRC_GRP_23_RSRC_TYPE_n)

		return;



	IPA_SETFIELD_IN_REG(*val, grp->y_min,

		IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MIN_LIM_SHFT_V3_5,

		IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MIN_LIM_BMSK_V3_5);

	IPA_SETFIELD_IN_REG(*val, grp->y_max,

		IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_SHFT_V3_5,

		IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_BMSK_V3_5);

}



static void ipareg_construct_hash_cfg_n(

	enum ipahal_reg_name reg, const void *fields, u32 *val)

{
@@ -423,13 +471,19 @@ static void ipareg_construct_debug_cnt_ctrl_n( 
		IPA_DEBUG_CNT_CTRL_n_DBG_CNT_SOURCE_PIPE_SHFT,

		IPA_DEBUG_CNT_CTRL_n_DBG_CNT_SOURCE_PIPE_BMSK);



	if (ipahal_ctx->hw_type <= IPA_HW_v3_1) {

		IPA_SETFIELD_IN_REG(*val, dbg_cnt_ctrl->rule_idx,

			IPA_DEBUG_CNT_CTRL_n_DBG_CNT_RULE_INDEX_SHFT,

			IPA_DEBUG_CNT_CTRL_n_DBG_CNT_RULE_INDEX_BMSK);



		IPA_SETFIELD_IN_REG(*val, dbg_cnt_ctrl->rule_idx_pipe_rule,

			IPA_DEBUG_CNT_CTRL_n_DBG_CNT_RULE_INDEX_PIPE_RULE_SHFT,

		IPA_DEBUG_CNT_CTRL_n_DBG_CNT_RULE_INDEX_PIPE_RULE_BMSK);

			IPA_DEBUG_CNT_CTRL_n_DBG_CNT_RULE_INDEX_PIPE_RULE_BMSK

			);

	} else {

		IPA_SETFIELD_IN_REG(*val, dbg_cnt_ctrl->rule_idx,

			IPA_DEBUG_CNT_CTRL_n_DBG_CNT_RULE_INDEX_SHFT,

			IPA_DEBUG_CNT_CTRL_n_DBG_CNT_RULE_INDEX_BMSK_V3_5);

	}

}



static void ipareg_parse_shared_mem_size(
@@ -459,6 +513,17 @@ static void ipareg_construct_endp_init_rsrc_grp_n( 
		IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK);

}



static void ipareg_construct_endp_init_rsrc_grp_n_v3_5(

		enum ipahal_reg_name reg, const void *fields, u32 *val)

{

	struct ipahal_reg_endp_init_rsrc_grp *rsrc_grp =

		(struct ipahal_reg_endp_init_rsrc_grp *)fields;



	IPA_SETFIELD_IN_REG(*val, rsrc_grp->rsrc_grp,

		IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT_v3_5,

		IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK_v3_5);

}



static void ipareg_construct_endp_init_hdr_metadata_n(

		enum ipahal_reg_name reg, const void *fields, u32 *val)

{
@@ -824,6 +889,26 @@ static void ipareg_construct_qsb_max_reads(enum ipahal_reg_name reg, 
			    IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_BMSK);

}



static void ipareg_construct_tx_cfg(enum ipahal_reg_name reg,

	const void *fields, u32 *val)

{

	struct ipahal_reg_tx_cfg *tx_cfg;



	tx_cfg = (struct ipahal_reg_tx_cfg *)fields;



	IPA_SETFIELD_IN_REG(*val, tx_cfg->tx0_prefetch_disable,

		IPA_TX_CFG_TX0_PREFETCH_DISABLE_SHFT_V3_5,

		IPA_TX_CFG_TX0_PREFETCH_DISABLE_BMSK_V3_5);



	IPA_SETFIELD_IN_REG(*val, tx_cfg->tx1_prefetch_disable,

		IPA_TX_CFG_TX1_PREFETCH_DISABLE_SHFT_V3_5,

		IPA_TX_CFG_TX1_PREFETCH_DISABLE_BMSK_V3_5);



	IPA_SETFIELD_IN_REG(*val, tx_cfg->prefetch_almost_empty_size,

		IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_SHFT_V3_5,

		IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_BMSK_V3_5);

}



/*

 * struct ipahal_reg_obj - Register H/W information for specific IPA version

 * @construct - CB to construct register value from abstracted structure
@@ -955,9 +1040,6 @@ static struct ipahal_reg_obj ipahal_reg_objs[IPA_HW_MAX][IPA_REG_MAX] = { 
		ipareg_construct_endp_init_hdr_metadata_n,

		ipareg_parse_dummy,

		0x0000081c, 0x70},

	[IPA_HW_v3_0][IPA_ENABLE_GSI] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		0x5500, 0},

	[IPA_HW_v3_0][IPA_ENDP_INIT_RSRC_GRP_n] = {

		ipareg_construct_endp_init_rsrc_grp_n,

		ipareg_parse_dummy,
@@ -1049,6 +1131,60 @@ static struct ipahal_reg_obj ipahal_reg_objs[IPA_HW_MAX][IPA_REG_MAX] = { 
	[IPA_HW_v3_1][IPA_SUSPEND_IRQ_CLR_EE_n] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		0x00003038, 0x1000},





	/* IPAv3.5 */

	[IPA_HW_v3_5][IPA_TX_CFG] = {

		ipareg_construct_tx_cfg, ipareg_parse_dummy,

		0x000001FC, 0},

	[IPA_HW_v3_5][IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n] = {

		ipareg_construct_rsrg_grp_xy_v3_5, ipareg_parse_dummy,

		0x00000400, 0x20},

	[IPA_HW_v3_5][IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n] = {

		ipareg_construct_rsrg_grp_xy_v3_5, ipareg_parse_dummy,

		0x00000404, 0x20},

	[IPA_HW_v3_5][IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		-1, 0},

	[IPA_HW_v3_5][IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		-1, 0},

	[IPA_HW_v3_5][IPA_DST_RSRC_GRP_01_RSRC_TYPE_n] = {

		ipareg_construct_rsrg_grp_xy_v3_5, ipareg_parse_dummy,

		0x00000500, 0x20},

	[IPA_HW_v3_5][IPA_DST_RSRC_GRP_23_RSRC_TYPE_n] = {

		ipareg_construct_rsrg_grp_xy_v3_5, ipareg_parse_dummy,

		0x00000504, 0x20},

	[IPA_HW_v3_5][IPA_DST_RSRC_GRP_45_RSRC_TYPE_n] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		-1, 0},

	[IPA_HW_v3_5][IPA_DST_RSRC_GRP_67_RSRC_TYPE_n] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		-1, 0},

	[IPA_HW_v3_5][IPA_ENDP_INIT_RSRC_GRP_n] = {

		ipareg_construct_endp_init_rsrc_grp_n_v3_5,

		ipareg_parse_dummy,

		0x00000838, 0x70},

	[IPA_HW_v3_5][IPA_RX_HPS_CLIENTS_MIN_DEPTH_0] = {

		ipareg_construct_rx_hps_clients_depth0_v3_5,

		ipareg_parse_dummy,

		0x000023C4, 0},

	[IPA_HW_v3_5][IPA_RX_HPS_CLIENTS_MIN_DEPTH_1] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		-1, 0},

	[IPA_HW_v3_5][IPA_RX_HPS_CLIENTS_MAX_DEPTH_0] = {

		ipareg_construct_rx_hps_clients_depth0_v3_5,

		ipareg_parse_dummy,

		0x000023CC, 0},

	[IPA_HW_v3_5][IPA_RX_HPS_CLIENTS_MAX_DEPTH_1] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		-1, 0},

	[IPA_HW_v3_5][IPA_SPARE_REG_1] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		0x00002780, 0},

	[IPA_HW_v3_5][IPA_SPARE_REG_2] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		0x00002784, 0},

};



/*
@@ -1334,22 +1470,29 @@ u32 ipahal_aggr_get_max_pkt_limit(void) 
		IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_SHFT;

}





void ipahal_get_aggr_force_close_valmask(int ep_idx,

	struct ipahal_reg_valmask *valmask)

{

	u32 shft;

	u32 bmsk;



	if (!valmask) {

		IPAHAL_ERR("Input error\n");

		return;

	}



	IPA_SETFIELD_IN_REG(valmask->val, 1 << ep_idx,

		IPA_AGGR_FORCE_CLOSE_OFST_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT,

		IPA_AGGR_FORCE_CLOSE_OFST_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK);

	if (ipahal_ctx->hw_type <= IPA_HW_v3_1) {

		shft = IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT;

		bmsk = IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK;

	} else {

		shft =

		IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V3_5;

		bmsk =

		IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_V3_5;

	}



	valmask->mask =

		IPA_AGGR_FORCE_CLOSE_OFST_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK <<

		IPA_AGGR_FORCE_CLOSE_OFST_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT;

	IPA_SETFIELD_IN_REG(valmask->val, 1 << ep_idx, shft, bmsk);

	valmask->mask = bmsk << shft;

}



void ipahal_get_fltrt_hash_flush_valmask(

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h

+17 −4
Original line number Diff line number Diff line
@@ -56,7 +56,6 @@ enum ipahal_reg_name { 
	IPA_IRQ_EE_UC_n,

	IPA_ENDP_INIT_HDR_METADATA_MASK_n,

	IPA_ENDP_INIT_HDR_METADATA_n,

	IPA_ENABLE_GSI,

	IPA_ENDP_INIT_RSRC_GRP_n,

	IPA_SHARED_MEM_SIZE,

	IPA_SRAM_DIRECT_ACCESS_n,
@@ -83,6 +82,7 @@ enum ipahal_reg_name { 
	IPA_RX_HPS_CLIENTS_MAX_DEPTH_1,

	IPA_QSB_MAX_WRITES,

	IPA_QSB_MAX_READS,

	IPA_TX_CFG,

	IPA_REG_MAX,

};
@@ -116,7 +116,7 @@ struct ipahal_reg_endp_init_route { 
};



/*

 * struct ipahal_reg_endp_init_rsrc_grp - PA_ENDP_INIT_RSRC_GRP_n register

 * struct ipahal_reg_endp_init_rsrc_grp - IPA_ENDP_INIT_RSRC_GRP_n register

 * @rsrc_grp: Index of group for this ENDP. If this ENDP is a source-ENDP,

 *	index is for source-resource-group. If destination ENPD, index is

 *	for destination-resoruce-group.
@@ -231,7 +231,8 @@ enum ipahal_reg_dbg_cnt_type { 
 * @src_pipe - Specific Pipe to match. If FF, no need to match

 *	specific pipe

 * @rule_idx_pipe_rule - Global Rule or Pipe Rule. If pipe, then indicated by

 *	src_pipe

 *	src_pipe. Starting at IPA V3_5,

 *	no support on Global Rule. This field will be ignored.

 * @rule_idx - Rule index. Irrelevant for type General

 */

struct ipahal_reg_debug_cnt_ctrl {
@@ -240,7 +241,7 @@ struct ipahal_reg_debug_cnt_ctrl { 
	bool product;

	u8 src_pipe;

	bool rule_idx_pipe_rule;

	u8 rule_idx;

	u16 rule_idx;

};



/*
@@ -316,6 +317,18 @@ struct ipahal_reg_qcncm { 
	u32 undefined;

};



/*

 * struct ipahal_reg_tx_cfg - IPA TX_CFG register

 * @tx0_prefetch_disable: Disable prefetch on TX0

 * @tx1_prefetch_disable: Disable prefetch on TX1

 * @prefetch_almost_empty_size: Prefetch almost empty size

 */

struct ipahal_reg_tx_cfg {

	bool tx0_prefetch_disable;

	bool tx1_prefetch_disable;

	u16 prefetch_almost_empty_size;

};



/*

 * ipahal_reg_name_str() - returns string that represent the register

 * @reg_name: [in] register name

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg_i.h

+25 −2
Original line number Diff line number Diff line
@@ -89,8 +89,10 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type); 
#define IPA_ENDP_INIT_AGGR_n_AGGR_EN_SHFT 0x0



/* IPA_AGGR_FORCE_CLOSE register */

#define IPA_AGGR_FORCE_CLOSE_OFST_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK 0x3fffffff

#define IPA_AGGR_FORCE_CLOSE_OFST_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT 0

#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK 0x3fffffff

#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT 0

#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_BMSK_V3_5 0xfffff

#define IPA_AGGR_FORCE_CLOSE_AGGR_FORCE_CLOSE_PIPE_BITMAP_SHFT_V3_5 0



/* IPA_ENDP_INIT_ROUTE_n register */

#define IPA_ENDP_INIT_ROUTE_n_ROUTE_TABLE_INDEX_BMSK 0x1f
@@ -177,6 +179,8 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type); 
/* IPA_ENDP_INIT_RSRC_GRP_n register */

#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK 0x7

#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT 0

#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK_v3_5 0x3

#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT_v3_5 0



/* IPA_SHARED_MEM_SIZE register */

#define IPA_SHARED_MEM_SIZE_SHARED_MEM_BADDR_BMSK 0xffff0000
@@ -188,6 +192,7 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type); 
#define IPA_DEBUG_CNT_CTRL_n_DBG_CNT_RULE_INDEX_PIPE_RULE_BMSK 0x10000000

#define IPA_DEBUG_CNT_CTRL_n_DBG_CNT_RULE_INDEX_PIPE_RULE_SHFT 0x1c

#define IPA_DEBUG_CNT_CTRL_n_DBG_CNT_RULE_INDEX_BMSK 0x0ff00000

#define IPA_DEBUG_CNT_CTRL_n_DBG_CNT_RULE_INDEX_BMSK_V3_5 0x1ff00000

#define IPA_DEBUG_CNT_CTRL_n_DBG_CNT_RULE_INDEX_SHFT 0x14

#define IPA_DEBUG_CNT_CTRL_n_DBG_CNT_SOURCE_PIPE_BMSK 0x1f000

#define IPA_DEBUG_CNT_CTRL_n_DBG_CNT_SOURCE_PIPE_SHFT 0xc
@@ -271,9 +276,20 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type); 
#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MAX_LIM_SHFT 8

#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_BMSK 0xFF

#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_SHFT 0

#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_BMSK_V3_5 0x3F000000

#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MAX_LIM_SHFT_V3_5 24

#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MIN_LIM_BMSK_V3_5 0x3F0000

#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_Y_MIN_LIM_SHFT_V3_5 16

#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MAX_LIM_BMSK_V3_5 0x3F00

#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MAX_LIM_SHFT_V3_5 8

#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_BMSK_V3_5 0x3F

#define IPA_RSRC_GRP_XY_RSRC_TYPE_n_X_MIN_LIM_SHFT_V3_5 0





/* IPA_IPA_IPA_RX_HPS_CLIENTS_MIN/MAX_DEPTH_0/1 registers */

#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_BMSK(n) (0x7F << (8 * (n)))

#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_BMSK_V3_5(n) \

						(0xF << (8 * (n)))

#define IPA_RX_HPS_CLIENTS_MINMAX_DEPTH_X_CLIENT_n_SHFT(n) (8 * (n))



/* IPA_QSB_MAX_WRITES register */
@@ -288,5 +304,12 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type); 
#define IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_BMSK (0xf0)

#define IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_SHFT (4)



/* IPA_TX_CFG register */

#define IPA_TX_CFG_TX0_PREFETCH_DISABLE_BMSK_V3_5 (0x1)

#define IPA_TX_CFG_TX0_PREFETCH_DISABLE_SHFT_V3_5 (0)

#define IPA_TX_CFG_TX1_PREFETCH_DISABLE_BMSK_V3_5 (0x2)

#define IPA_TX_CFG_TX1_PREFETCH_DISABLE_SHFT_V3_5 (1)

#define IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_BMSK_V3_5 (0x1C)

#define IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_SHFT_V3_5 (2)



#endif /* _IPAHAL_REG_I_H_ */