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Commit 8422d1f1 authored by David S. Miller's avatar David S. Miller
Browse files


John W. Linville says:

====================
pull request: wireless 2013-11-14

Please pull this batch of fixes intended for the 3.13 stream!

Amitkumar Karwar offers a quartet of mwifiex fixes, including an
endian fix and three fixes for invalid memory access.

Avinash Patil trims the packet length value for packets received from
an SDIO interface.

Colin Ian King fixes a NULL pointer dereference in the rtlwifi
efuse code.

Dan Carpenter cleans-up an mwifiex integer underflow, a potential
libertas oops, a memory corrupion bug in wcn36xx, and a locking issue
also in wcn36xx.

Dan Williams helps prism54 devices to avoid being misclassified as
Ethernet devices.

Felipe Pena fixes a couple of typo errors, one in rt2x00 and the
other in rtlwifi.

Janusz Dziedzic corrects a pair of DFS-related problems in ath9k.

Larry Finger patches three rtlwifi drivers to correctly report signal
strength even for an unassociated AP.

Mark Cave-Ayland rewrites some endian-illiterate packet type extraction
code in rtlwifi.

Stanislaw Gruszka addresses an rt2x00 regression related to setting
HT station WCID and AMPDU density parameters.

Sujith Manoharan corrects the initvals settings for AR9485.

Ujjal Roy patches an obscure bit of code in mwifiex that was using
the wrong definition of eth_hdr when briding patches in AP mode.

Wei Yongjun fixes a couple of bugs: one is a return code handling
bug in libertas; and, the other is a locking issue in wcn36xx.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 5061de36 d8ec5a5d
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+11 −11
Original line number Diff line number Diff line
@@ -187,17 +187,17 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
		INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
			       ar9485_1_1_baseband_core_txfir_coeff_japan_2484);

		/* Load PCIE SERDES settings from INI */

		/* Awake Setting */

		if (ah->config.no_pll_pwrsave) {
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
				       ar9485_1_1_pcie_phy_clkreq_disable_L1);

		/* Sleep Setting */

			INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
				       ar9485_1_1_pcie_phy_clkreq_disable_L1);
		} else {
			INIT_INI_ARRAY(&ah->iniPcieSerdes,
				       ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
			INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
				       ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
		}
	} else if (AR_SREV_9462_21(ah)) {
		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
			       ar9462_2p1_mac_core);
+14 −28
Original line number Diff line number Diff line
@@ -32,13 +32,6 @@ static const u32 ar9485_1_1_mac_postamble[][5] = {
	{0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
};

static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1[][2] = {
	/* Addr      allmodes  */
	{0x00018c00, 0x18012e5e},
	{0x00018c04, 0x000801d8},
	{0x00018c08, 0x0000080c},
};

static const u32 ar9485Common_wo_xlna_rx_gain_1_1[][2] = {
	/* Addr      allmodes  */
	{0x00009e00, 0x037216a0},
@@ -1101,20 +1094,6 @@ static const u32 ar9485_common_rx_gain_1_1[][2] = {
	{0x0000a1fc, 0x00000296},
};

static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_enable_L1[][2] = {
	/* Addr      allmodes  */
	{0x00018c00, 0x18052e5e},
	{0x00018c04, 0x000801d8},
	{0x00018c08, 0x0000080c},
};

static const u32 ar9485_1_1_pcie_phy_clkreq_enable_L1[][2] = {
	/* Addr      allmodes  */
	{0x00018c00, 0x18053e5e},
	{0x00018c04, 0x000801d8},
	{0x00018c08, 0x0000080c},
};

static const u32 ar9485_1_1_soc_preamble[][2] = {
	/* Addr      allmodes  */
	{0x00004014, 0xba280400},
@@ -1173,13 +1152,6 @@ static const u32 ar9485_1_1_baseband_postamble[][5] = {
	{0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
};

static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
	/* Addr      allmodes  */
	{0x00018c00, 0x18013e5e},
	{0x00018c04, 0x000801d8},
	{0x00018c08, 0x0000080c},
};

static const u32 ar9485_1_1_radio_postamble[][2] = {
	/* Addr      allmodes  */
	{0x0001609c, 0x0b283f31},
@@ -1358,4 +1330,18 @@ static const u32 ar9485_1_1_baseband_core_txfir_coeff_japan_2484[][2] = {
	{0x0000a3a0, 0xca9228ee},
};

static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
	/* Addr      allmodes  */
	{0x00018c00, 0x18013e5e},
	{0x00018c04, 0x000801d8},
	{0x00018c08, 0x0000080c},
};

static const u32 ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1[][2] = {
	/* Addr      allmodes  */
	{0x00018c00, 0x1801265e},
	{0x00018c04, 0x000801d8},
	{0x00018c08, 0x0000080c},
};

#endif /* INITVALS_9485_H */
+10 −9
Original line number Diff line number Diff line
@@ -641,6 +641,7 @@ void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs);
#define ATH9K_PCI_D3_L1_WAR       0x0040
#define ATH9K_PCI_AR9565_1ANT     0x0080
#define ATH9K_PCI_AR9565_2ANT     0x0100
#define ATH9K_PCI_NO_PLL_PWRSAVE  0x0200

/*
 * Default cache line size, in bytes.
+10 −3
Original line number Diff line number Diff line
@@ -44,14 +44,20 @@ static ssize_t read_file_dfs(struct file *file, char __user *user_buf,
	if (buf == NULL)
		return -ENOMEM;

	if (sc->dfs_detector)
		dfs_pool_stats = sc->dfs_detector->get_stats(sc->dfs_detector);

	len += scnprintf(buf + len, size - len, "DFS support for "
			 "macVersion = 0x%x, macRev = 0x%x: %s\n",
			 hw_ver->macVersion, hw_ver->macRev,
			 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_DFS) ?
					"enabled" : "disabled");

	if (!sc->dfs_detector) {
		len += scnprintf(buf + len, size - len,
				 "DFS detector not enabled\n");
		goto exit;
	}

	dfs_pool_stats = sc->dfs_detector->get_stats(sc->dfs_detector);

	len += scnprintf(buf + len, size - len, "Pulse detector statistics:\n");
	ATH9K_DFS_STAT("pulse events reported   ", pulses_total);
	ATH9K_DFS_STAT("invalid pulse events    ", pulses_no_dfs);
@@ -76,6 +82,7 @@ static ssize_t read_file_dfs(struct file *file, char __user *user_buf,
	ATH9K_DFS_POOL_STAT("Seqs. alloc error       ", pseq_alloc_error);
	ATH9K_DFS_POOL_STAT("Seqs. in use            ", pseq_used);

exit:
	if (len > size)
		len = size;

+1 −0
Original line number Diff line number Diff line
@@ -316,6 +316,7 @@ struct ath9k_ops_config {
	u32 ant_ctrl_comm2g_switch_enable;
	bool xatten_margin_cfg;
	bool alt_mingainidx;
	bool no_pll_pwrsave;
};

enum ath9k_int {
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