Loading arch/arm/boot/dts/qcom/msmcobalt.dtsi +55 −0 Original line number Diff line number Diff line Loading @@ -896,6 +896,61 @@ qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>; }; pil_modem: qcom,mss@4080000 { compatible = "qcom,pil-q6v55-mss"; reg = <0x4080000 0x100>, <0x1f63000 0x008>, <0x1f65000 0x008>, <0x1f64000 0x008>, <0x4180000 0x020>, <0x00179000 0x004>; reg-names = "qdsp6_base", "halt_q6", "halt_modem", "halt_nc", "rmb_base", "restart_reg"; clocks = <&clock_gcc clk_cxo_clk_src>, <&clock_gcc clk_gcc_mss_cfg_ahb_clk>, <&clock_gcc clk_pnoc_clk>, <&clock_gcc clk_gcc_mss_q6_bimc_axi_clk>, <&clock_gcc clk_gcc_boot_rom_ahb_clk>, <&clock_gcc clk_gpll0_out_msscc>, <&clock_gcc clk_gcc_mss_snoc_axi_clk>, <&clock_gcc clk_gcc_mss_mnoc_bimc_axi_clk>, <&clock_gcc clk_qdss_clk>; clock-names = "xo", "iface_clk", "pnoc_clk", "bus_clk", "mem_clk", "gpll0_mss_clk", "snoc_axi_clk", "mnoc_axi_clk", "qdss_clk"; qcom,proxy-clock-names = "xo", "pnoc_clk", "qdss_clk"; qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk", "gpll0_mss_clk", "snoc_axi_clk", "mnoc_axi_clk"; interrupts = <0 448 1>; vdd_cx-supply = <&pmcobalt_s1_level>; vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>; vdd_mx-supply = <&pmcobalt_s9_level>; vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>; vdd_pll-supply = <&pm8005_s3>; qcom,vdd_pll = <600000>; qcom,firmware-name = "modem"; qcom,pil-self-auth; qcom,sysmon-id = <0>; qcom,ssctl-instance-id = <0x12>; qcom,override-acc; qcom,qdsp6v62-1-2; memory-region = <&modem_mem>; qcom,mem-protect-id = <0xF>; /* GPIO inputs from mss */ qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>; qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>; qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>; qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>; qcom,gpio-shutdown-ack = <&smp2pgpio_ssr_smp2p_1_in 7 0>; /* GPIO output to mss */ qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>; }; qcom,sensor-information { compatible = "qcom,sensor-information"; sensor_information0: qcom,sensor-information-0 { Loading Loading
arch/arm/boot/dts/qcom/msmcobalt.dtsi +55 −0 Original line number Diff line number Diff line Loading @@ -896,6 +896,61 @@ qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>; }; pil_modem: qcom,mss@4080000 { compatible = "qcom,pil-q6v55-mss"; reg = <0x4080000 0x100>, <0x1f63000 0x008>, <0x1f65000 0x008>, <0x1f64000 0x008>, <0x4180000 0x020>, <0x00179000 0x004>; reg-names = "qdsp6_base", "halt_q6", "halt_modem", "halt_nc", "rmb_base", "restart_reg"; clocks = <&clock_gcc clk_cxo_clk_src>, <&clock_gcc clk_gcc_mss_cfg_ahb_clk>, <&clock_gcc clk_pnoc_clk>, <&clock_gcc clk_gcc_mss_q6_bimc_axi_clk>, <&clock_gcc clk_gcc_boot_rom_ahb_clk>, <&clock_gcc clk_gpll0_out_msscc>, <&clock_gcc clk_gcc_mss_snoc_axi_clk>, <&clock_gcc clk_gcc_mss_mnoc_bimc_axi_clk>, <&clock_gcc clk_qdss_clk>; clock-names = "xo", "iface_clk", "pnoc_clk", "bus_clk", "mem_clk", "gpll0_mss_clk", "snoc_axi_clk", "mnoc_axi_clk", "qdss_clk"; qcom,proxy-clock-names = "xo", "pnoc_clk", "qdss_clk"; qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk", "gpll0_mss_clk", "snoc_axi_clk", "mnoc_axi_clk"; interrupts = <0 448 1>; vdd_cx-supply = <&pmcobalt_s1_level>; vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>; vdd_mx-supply = <&pmcobalt_s9_level>; vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>; vdd_pll-supply = <&pm8005_s3>; qcom,vdd_pll = <600000>; qcom,firmware-name = "modem"; qcom,pil-self-auth; qcom,sysmon-id = <0>; qcom,ssctl-instance-id = <0x12>; qcom,override-acc; qcom,qdsp6v62-1-2; memory-region = <&modem_mem>; qcom,mem-protect-id = <0xF>; /* GPIO inputs from mss */ qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>; qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>; qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>; qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>; qcom,gpio-shutdown-ack = <&smp2pgpio_ssr_smp2p_1_in 7 0>; /* GPIO output to mss */ qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>; }; qcom,sensor-information { compatible = "qcom,sensor-information"; sensor_information0: qcom,sensor-information-0 { Loading