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Commit 83bc10a2 authored by Punit Agrawal's avatar Punit Agrawal Committed by Will Deacon
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ARM: dts: Document the CCI PMU DT bindings 



The CCI PMU can profile bus transactions at the master and slave
interfaces of the CCI. The PMU can be used to observe an aggregated
view of the bus traffic between the various components connected to the
CCI.

Introduce a binding for the CCI PMU. The PMU node will be a sub-node of
the CCI node.

Cc: devicetree@vger.kernel.org
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Acked-by: default avatarStephen Warren <swarren@nvidia.com>
Acked-by: default avatarKumar Gala <galak@codeaurora.org>
Signed-off-by: default avatarPunit Agrawal <punit.agrawal@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent fcb20f15

Documentation/devicetree/bindings/arm/cci.txt

+47 −1
Original line number Original line Diff line number Diff line
@@ -85,6 +85,42 @@ specific to ARM. 
				    corresponding interface programming

				    corresponding interface programming

				    registers.

				    registers.





	- CCI PMU node



		Parent node must be CCI interconnect node.



		A CCI pmu node must contain the following properties:



		- compatible

			Usage: required

			Value type: <string>

			Definition: must be "arm,cci-400-pmu"



		- reg:

			Usage: required

			Value type: Integer cells. A register entry, expressed

				    as a pair of cells, containing base and

				    size.

			Definition: the base address and size of the

				    corresponding interface programming

				    registers.



		- interrupts:

			Usage: required

			Value type: Integer cells. Array of interrupt specifier

				    entries, as defined in

				    ../interrupt-controller/interrupts.txt.

			Definition: list of counter overflow interrupts, one per

				    counter. The interrupts must be specified

				    starting with the cycle counter overflow

				    interrupt, followed by counter0 overflow

				    interrupt, counter1 overflow interrupt,...

				    ,counterN overflow interrupt.



				    The CCI PMU has an interrupt signal for each

				    counter. The number of interrupts must be

				    equal to the number of counters.



* CCI interconnect bus masters

* CCI interconnect bus masters





	Description: masters in the device tree connected to a CCI port

	Description: masters in the device tree connected to a CCI port
@@ -150,7 +186,7 @@ Example: 
		#address-cells = <1>;

		#address-cells = <1>;

		#size-cells = <1>;

		#size-cells = <1>;

		reg = <0x0 0x2c090000 0 0x1000>;

		reg = <0x0 0x2c090000 0 0x1000>;

		ranges = <0x0 0x0 0x2c090000 0x6000>;

		ranges = <0x0 0x0 0x2c090000 0x10000>;





		cci_control0: slave-if@1000 {

		cci_control0: slave-if@1000 {

			compatible = "arm,cci-400-ctrl-if";

			compatible = "arm,cci-400-ctrl-if";
@@ -169,6 +205,16 @@ Example: 
			interface-type = "ace";

			interface-type = "ace";

			reg = <0x5000 0x1000>;

			reg = <0x5000 0x1000>;

		};

		};



		pmu@9000 {

			 compatible = "arm,cci-400-pmu";

			 reg = <0x9000 0x5000>;

			 interrupts = <0 101 4>,

				      <0 102 4>,

				      <0 103 4>,

				      <0 104 4>,

				      <0 105 4>;

		};

	};

	};





This CCI node corresponds to a CCI component whose control registers sits

This CCI node corresponds to a CCI component whose control registers sits