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Commit 83646423 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "dwc3: Move usage of ahb2phy read/write wait functionality to controller"

parents b7ea9a96 a539b41f

Documentation/devicetree/bindings/usb/msm-phy.txt

+1 −4
Original line number Diff line number Diff line
@@ -19,7 +19,7 @@ Required properties: 
Optional properties:

 - reg: Additional registers

	"tcsr" : top-level CSR register to be written during power-on reset

		 intialize the internal MUX that controls whether this PHY is

		 initialize the internal MUX that controls whether this PHY is

		 used with the USB3 or the USB2 controller.



 - qcom,hsphy-init: Init value used to override HSPHY parameters into
@@ -98,7 +98,6 @@ Required properties: 
 - reg: Address and length of the register set for the device

   Required regs are:

   "qmp_phy_base" : QMP PHY Base register set.

   "qmp_ahb2phy_base" : SS AHB2PHY CSR register set.

 - "vls_clamp_reg" : top-level CSR register to be written to enable phy vls

   clamp which allows phy to detect autonomous mode.

 - <supply-name>-supply: phandle to the regulator device tree node
@@ -121,10 +120,8 @@ Example: 
	ssphy0: ssphy@f9b38000 {

		compatible = "qcom,usb-ssphy-qmp";

		reg = <0xf9b38000 0x16c>,

			<0xf9b3e000 0x3ff>,

			<0x01947244 0x4>;

		reg-names = "qmp_phy_base",

			"qmp_ahb2phy_base",

			"vls_clamp_reg";

		vdd-supply = <&pmd9635_l4>;

		vdda18-supply = <&pmd9635_l8>;

Documentation/devicetree/bindings/usb/msm-ssusb.txt

+14 −4
Original line number Diff line number Diff line
@@ -2,9 +2,9 @@ MSM SuperSpeed USB3.0 SoC controller 


Required properties :

- compatible : should be "qcom,dwc-usb3-msm"

- reg : offset and length of the register set in the memory map

	offset and length of the TCSR register for routing USB

	signals to either picoPHY0 or picoPHY1.

 - reg: Address and length of the register set for the device

   Required regs are:

	"core_base" : usb controller register set

- interrupts: IRQ lines used by this controller

- interrupt-names : Interrupt resource entries are :

	"hs_phy_irq" : Interrupt from HS PHY for asynchronous events in LPM.
@@ -17,6 +17,12 @@ Required properties : 
	'dwc3' sub node for "DWC3-USB3 Core device".



Optional properties :

- reg: Additional registers

     "tcsr_base" : top-level CSR register to be written during power-on reset

     initialize the internal MUX that controls whether to use USB3 controller

     with primary port.

     "ahb2phy_base" : top-level register to configure read/write wait cycle with

     both QMP and QUSB PHY registers.

- Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for

  below optional properties:

    - qcom,msm_bus,name
@@ -50,7 +56,11 @@ Example MSM USB3.0 controller device node : 
	usb@f9200000 {

		compatible = "qcom,dwc-usb3-msm";

		reg = <0xf9200000 0xfc000>,

		      <0xfd4ab000 0x4>;

		      <0xfd4ab000 0x4>,

		      <0xf9b3e000 0x3ff>;

		reg-names = "core_base",

			"tcsr_base",

			"ahb2phy_base",

		interrupts = <0 133 0>;

		interrupt-names = "hs_phy_irq";

		vbus_dwc3-supply = <&pm8941_mvs1>;

arch/arm/boot/dts/qcom/mdm9640.dtsi

+5 −5
Original line number Diff line number Diff line
@@ -609,7 +609,9 @@ 


	usb3: ssusb@8a00000{

		compatible = "qcom,dwc-usb3-msm";

		reg = <0x08a00000 0xfc000>;

		reg = <0x08a00000 0xfc000>,

			<0x0007e000 0x400>;

		reg-names = "core_base", "ahb2phy_base";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;
@@ -803,10 +805,8 @@ 


	ssphy: ssphy@78000 {

		compatible = "qcom,usb-ssphy-qmp";

		reg = <0x00078000 0x45c>,

		      <0x0007e000 0x400>;

		reg-names = "qmp_phy_base",

			    "qmp_ahb2phy_base";

		reg = <0x00078000 0x45c>;

		reg-names = "qmp_phy_base";

		vdd-supply = <&pmd9635_l4>;

		vdda18-supply = <&pmd9635_l8>;

		qcom,vdd-voltage-level = <0 1000000 1000000>;

arch/arm/boot/dts/qcom/mdmcalifornium.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -490,7 +490,9 @@ 


	usb3: ssusb@8a00000 {

		compatible = "qcom,dwc-usb3-msm";

		reg = <0x08a00000 0xf8c00>;

		reg = <0x08a00000 0xf8c00>,

			<0x0007e000 0x400>;

		reg-names = "core_base", "ahb2phy_base";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;
@@ -569,10 +571,8 @@ 
	ssphy: ssphy@78000 {

		compatible = "qcom,usb-ssphy-qmp";

		reg = <0x00078000 0x45c>,

		      <0x0007e000 0x400>,

		      <0x01947244 0x4>;

		reg-names = "qmp_phy_base",

			    "qmp_ahb2phy_base",

			    "vls_clamp_reg";

		vdd-supply = <&pmdcalifornium_l4>;

		vdda18-supply = <&pmdcalifornium_l5>;

arch/arm/boot/dts/qcom/msm8996.dtsi

+8 −4
Original line number Diff line number Diff line
@@ -1813,7 +1813,10 @@ 


	usb3: ssusb@6a00000{

		compatible = "qcom,dwc-usb3-msm";

		reg = <0x06a00000 0xfc000>;

		reg = <0x06a00000 0xfc000>,

			<0x7416000 0x400>;

		reg-names = "core_base",

			"ahb2phy_base";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;
@@ -1923,7 +1926,10 @@ 


	usb2s: hsusb@7600000 {

		compatible = "qcom,dwc-usb3-msm";

		reg = <0x07600000 0xfc000>;

		reg = <0x07600000 0xfc000>,

			<0x7416000 0x400>;

		reg-names = "core_base",

			"ahb2phy_base";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;
@@ -2035,10 +2041,8 @@ 
	ssphy: ssphy@7410000 {

		compatible = "qcom,usb-ssphy-qmp-v2";

		reg = <0x7410000 0x45C>,

		      <0x7416000 0x400>,

		      <0x007AB244 0x4>;

		reg-names = "qmp_phy_base",

			    "qmp_ahb2phy_base",

			    "vls_clamp_reg";

		vdd-supply = <&pm8994_l28>;

		vdda18-supply = <&pm8994_l12>;