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Commit 8327eb65 authored by Deepak SIKRI's avatar Deepak SIKRI Committed by David S. Miller
Browse files

stmmac: re-work the internal GMAC DMA platf parameters 



This patch re-works the internal GMAC DMA parameters
passed from the platform.
In the past, we only passed the pbl but, with new core,
other parameters can be passed and are mandatory on some
platforms.

New parameters are documented in stmmac.txt because this
patch has an impact for many platforms.

Signed-off-by: default avatarShiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: default avatarVikas Manocha <vikas.manocha@st.com>
Signed-off-by: default avatarDeepak Sikri <deepak.sikri@st.com>
Hacked-by: default avatarGiuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent faeae3fa

Documentation/networking/stmmac.txt

+21 −3
Original line number Diff line number Diff line
@@ -111,7 +111,7 @@ and detailed below as well: 
	int phy_addr;

	int interface;

	struct stmmac_mdio_bus_data *mdio_bus_data;

	int pbl;

	struct stmmac_dma_cfg *dma_cfg;

	int clk_csr;

	int has_gmac;

	int enh_desc;
@@ -163,7 +163,7 @@ Where: 
 o custom_cfg: this is a custom configuration that can be passed while

	      initialising the resources.



The we have:

For MDIO bus The we have:



 struct stmmac_mdio_bus_data {

	int bus_id;
@@ -180,10 +180,28 @@ Where: 
 o irqs: list of IRQs, one per PHY.

 o probed_phy_irq: if irqs is NULL, use this for probed PHY.





For DMA engine we have the following internal fields that should be

tuned according to the HW capabilities.



struct stmmac_dma_cfg {

	int pbl;

	int fixed_burst;

	int burst_len_supported;

};



Where:

 o pbl: Programmable Burst Length

 o fixed_burst: program the DMA to use the fixed burst mode

 o burst_len: this is the value we put in the register

	      supported values are provided as macros in

	      linux/stmmac.h header file.



---



Below an example how the structures above are using on ST platforms.



 static struct plat_stmmacenet_data stxYYY_ethernet_platform_data = {

	.pbl = 32,

	.has_gmac = 0,

	.enh_desc = 0,

	.fix_mac_speed = stxYYY_ethernet_fix_mac_speed,

drivers/net/ethernet/stmicro/stmmac/common.h

+2 −1
Original line number Diff line number Diff line
@@ -236,7 +236,8 @@ struct stmmac_desc_ops { 


struct stmmac_dma_ops {

	/* DMA core initialization */

	int (*init) (void __iomem *ioaddr, int pbl, u32 dma_tx, u32 dma_rx);

	int (*init) (void __iomem *ioaddr, int pbl, int fb, int burst_len,

			u32 dma_tx, u32 dma_rx);

	/* Dump DMA registers */

	void (*dump_regs) (void __iomem *ioaddr);

	/* Set tx/rx threshold in the csr6 register

drivers/net/ethernet/stmicro/stmmac/dwmac1000.h

+1 −1
Original line number Diff line number Diff line
@@ -142,7 +142,7 @@ enum rx_tx_priority_ratio { 
#define DMA_BUS_MODE_RPBL_MASK	0x003e0000	/* Rx-Programmable Burst Len */

#define DMA_BUS_MODE_RPBL_SHIFT	17

#define DMA_BUS_MODE_USP	0x00800000

#define DMA_BUS_MODE_4PBL	0x01000000

#define DMA_BUS_MODE_PBL	0x01000000

#define DMA_BUS_MODE_AAL	0x02000000



/* DMA CRS Control and Status Register Mapping */

drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c

+37 −5
Original line number Diff line number Diff line
@@ -30,8 +30,8 @@ 
#include "dwmac1000.h"

#include "dwmac_dma.h"



static int dwmac1000_dma_init(void __iomem *ioaddr, int pbl, u32 dma_tx,

			      u32 dma_rx)

static int dwmac1000_dma_init(void __iomem *ioaddr, int pbl, int fb,

			      int burst_len, u32 dma_tx, u32 dma_rx)

{

	u32 value = readl(ioaddr + DMA_BUS_MODE);

	int limit;
@@ -48,15 +48,47 @@ static int dwmac1000_dma_init(void __iomem *ioaddr, int pbl, u32 dma_tx, 
	if (limit < 0)

		return -EBUSY;



	value = /* DMA_BUS_MODE_FB | */ DMA_BUS_MODE_4PBL |

	    ((pbl << DMA_BUS_MODE_PBL_SHIFT) |

	/*

	 * Set the DMA PBL (Programmable Burst Length) mode

	 * Before stmmac core 3.50 this mode bit was 4xPBL, and

	 * post 3.5 mode bit acts as 8*PBL.

	 * For core rev < 3.5, when the core is set for 4xPBL mode, the

	 * DMA transfers the data in 4, 8, 16, 32, 64 & 128 beats

	 * depending on pbl value.

	 * For core rev > 3.5, when the core is set for 8xPBL mode, the

	 * DMA transfers the data in 8, 16, 32, 64, 128 & 256 beats

	 * depending on pbl value.

	 */

	value = DMA_BUS_MODE_PBL | ((pbl << DMA_BUS_MODE_PBL_SHIFT) |

		(pbl << DMA_BUS_MODE_RPBL_SHIFT));



	/* Set the Fixed burst mode */

	if (fb)

		value |= DMA_BUS_MODE_FB;



#ifdef CONFIG_STMMAC_DA

	value |= DMA_BUS_MODE_DA;	/* Rx has priority over tx */

#endif

	writel(value, ioaddr + DMA_BUS_MODE);



	/* In case of GMAC AXI configuration, program the DMA_AXI_BUS_MODE

	 * for supported bursts.

	 *

	 * Note: This is applicable only for revision GMACv3.61a. For

	 * older version this register is reserved and shall have no

	 * effect.

	 *

	 * Note:

	 *  For Fixed Burst Mode: if we directly write 0xFF to this

	 *  register using the configurations pass from platform code,

	 *  this would ensure that all bursts supported by core are set

	 *  and those which are not supported would remain ineffective.

	 *

	 *  For Non Fixed Burst Mode: provide the maximum value of the

	 *  burst length. Any burst equal or below the provided burst

	 *  length would be allowed to perform. */

	writel(burst_len, ioaddr + DMA_AXI_BUS_MODE);



	/* Mask interrupts by writing to CSR7 */

	writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);

drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c

+3 −3
Original line number Diff line number Diff line
@@ -32,8 +32,8 @@ 
#include "dwmac100.h"

#include "dwmac_dma.h"



static int dwmac100_dma_init(void __iomem *ioaddr, int pbl, u32 dma_tx,

			     u32 dma_rx)

static int dwmac100_dma_init(void __iomem *ioaddr, int pbl, int fb,

			     int burst_len, u32 dma_tx, u32 dma_rx)

{

	u32 value = readl(ioaddr + DMA_BUS_MODE);

	int limit;