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Commit 82aeef0b authored by Li, Zhen-Hua's avatar Li, Zhen-Hua Committed by Joerg Roedel
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x86/iommu: correct ICS register offset 



According to Intel Vt-D specs, the offset of Invalidation complete
status register should be 0x9C, not 0x98.

See Intel's VT-d spec, Revision 1.3, Chapter 10.4, Page 98;

Signed-off-by: default avatarLi, Zhen-Hua <zhen-hual@hp.com>
Signed-off-by: default avatarJoerg Roedel <joro@8bytes.org>
parent 0b6e8569

include/linux/intel-iommu.h

+1 −1
Original line number Diff line number Diff line
@@ -55,7 +55,7 @@ 
#define DMAR_IQT_REG	0x88	/* Invalidation queue tail register */

#define DMAR_IQ_SHIFT	4	/* Invalidation queue head/tail shift */

#define DMAR_IQA_REG	0x90	/* Invalidation queue addr register */

#define DMAR_ICS_REG	0x98	/* Invalidation complete status register */

#define DMAR_ICS_REG	0x9c	/* Invalidation complete status register */

#define DMAR_IRTA_REG	0xb8    /* Interrupt remapping table addr register */



#define OFFSET_STRIDE		(9)