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Commit 82432cea authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add qcom,clk-dis-wait-val value for msmthorium"

parents 61b2ca33 8eb27c63

Documentation/devicetree/bindings/arm/msm/clock-controller.txt

+3 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ Required properties: 
			"qcom,gcc-8996"

			"qcom,gcc-8996-v2"

			"qcom,gcc-8996-v3"

			"qcom,gcc-thorium"

			"qcom,rpmcc-8994"

			"qcom,rpmcc-8992"

			"qcom,rpmcc-8916"
@@ -37,10 +38,12 @@ Required properties: 
			"qcom,cc-debug-8996"

			"qcom,cc-debug-8996-v2"

			"qcom,cc-debug-8996-v3"

			"qcom,cc-debug-thorium"

			"qcom,gcc-mdss-8936"

			"qcom,gcc-mdss-8909"

			"qcom,gcc-mdss-8916"

			"qcom,gcc-mdss-8952"

			"qcom,gcc-mdss-thorium"

			"qcom,mmsscc-8994v2"

			"qcom,mmsscc-8994"

			"qcom,mmsscc-8992"

arch/arm/boot/dts/qcom/msmthorium.dtsi

+91 −2
Original line number Diff line number Diff line
@@ -296,8 +296,27 @@ 
		dma-names = "tx", "rx";

	};



	clock_gcc: qcom,gcc {

		compatible = "qcom,dummycc";

	clock_gcc: qcom,gcc@1800000 {

		compatible = "qcom,gcc-thorium";

		reg = <0x1800000 0x80000>,

			<0xb116000 0x00040>,

			<0xb016000 0x00040>,

			<0xb1d0000 0x00040>;

		reg-names = "cc_base", "apcs_c0_base",

			"apcs_c1_base", "apcs_cci_base";

		vdd_dig-supply = <&pmthorium_s2_level>;

		vdd_sr2_dig-supply = <&pmthorium_s2_level_ao>;

		vdd_sr2_pll-supply = <&pmthorium_l7_ao>;

		vdd_hf_dig-supply = <&pmthorium_s2_level_ao>;

		vdd_hf_pll-supply = <&pmthorium_l7_ao>;

		#clock-cells = <1>;

	};



	clock_debug: qcom,cc-debug@1874000 {

		compatible = "qcom,cc-debug-thorium";

		reg = <0x1874000 0x4>,

		      <0xb11101c 0x8>;

		reg-names = "cc_base", "meas";

		#clock-cells = <1>;

	};
@@ -787,3 +806,73 @@ 
#include "msmthorium-regulator.dtsi"

#include "msm-pmthorium.dtsi"

#include "msm-pmithorium.dtsi"

#include "msm-gdsc-8916.dtsi"



&gdsc_venus {

	clock-names = "bus_clk", "core_clk";

	clocks = <&clock_gcc clk_gcc_venus0_axi_clk>,

		 <&clock_gcc clk_gcc_venus0_vcodec0_clk>;

	status = "okay";

};



&gdsc_venus_core0 {

	qcom,support-hw-trigger;

	clock-names ="core0_clk";

	clocks = <&clock_gcc clk_gcc_venus0_core0_vcodec0_clk>;

	status = "okay";

};



&gdsc_mdss {

	clock-names = "core_clk", "bus_clk";

	clocks = <&clock_gcc clk_gcc_mdss_mdp_clk>,

		 <&clock_gcc clk_gcc_mdss_axi_clk>;

	status = "okay";

};



&gdsc_jpeg {

	clock-names = "core_clk", "bus_clk";

	clocks = <&clock_gcc clk_gcc_camss_jpeg0_clk>,

		 <&clock_gcc clk_gcc_camss_jpeg_axi_clk>;

	status = "okay";

};



&gdsc_vfe {

	clock-names = "core_clk", "bus_clk", "micro_clk",

			"csi_clk";

	clocks = <&clock_gcc clk_gcc_camss_vfe0_clk>,

		 <&clock_gcc clk_gcc_camss_vfe_axi_clk>,

		 <&clock_gcc clk_gcc_camss_micro_ahb_clk>,

		 <&clock_gcc clk_gcc_camss_csi_vfe0_clk>;

	status = "okay";

};



&gdsc_vfe1 {

	clock-names = "core_clk", "bus_clk", "micro_clk",

			"csi_clk";

	clocks = <&clock_gcc clk_gcc_camss_vfe1_clk>,

		 <&clock_gcc clk_gcc_camss_vfe1_axi_clk>,

		 <&clock_gcc clk_gcc_camss_micro_ahb_clk>,

		 <&clock_gcc clk_gcc_camss_csi_vfe1_clk>;

	status = "okay";

};



&gdsc_cpp {

	clock-names = "core_clk", "bus_clk";

	clocks = <&clock_gcc clk_gcc_camss_cpp_clk>,

		 <&clock_gcc clk_gcc_camss_cpp_axi_clk>;

	status = "okay";

};



&gdsc_oxili_gx {

	clock-names = "core_root_clk", "gmem_clk";

	clocks =<&clock_gcc clk_gfx3d_clk_src>,

		<&clock_gcc clk_gcc_oxili_gmem_clk>;

	qcom,enable-root-clk;

	qcom,clk-dis-wait-val = <0x5>;

	status = "okay";

};



&gdsc_oxili_cx {

	reg = <0x1859044 0x4>;

	status = "okay";

};