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Commit 82432cea authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add qcom,clk-dis-wait-val value for msmthorium"

parents 61b2ca33 8eb27c63

Documentation/devicetree/bindings/arm/msm/clock-controller.txt

+3 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ Required properties: 
			"qcom,gcc-8996"

			"qcom,gcc-8996-v2"

			"qcom,gcc-8996-v3"

			"qcom,gcc-thorium"

			"qcom,rpmcc-8994"

			"qcom,rpmcc-8992"

			"qcom,rpmcc-8916"
@@ -37,10 +38,12 @@ Required properties: 
			"qcom,cc-debug-8996"

			"qcom,cc-debug-8996-v2"

			"qcom,cc-debug-8996-v3"

			"qcom,cc-debug-thorium"

			"qcom,gcc-mdss-8936"

			"qcom,gcc-mdss-8909"

			"qcom,gcc-mdss-8916"

			"qcom,gcc-mdss-8952"

			"qcom,gcc-mdss-thorium"

			"qcom,mmsscc-8994v2"

			"qcom,mmsscc-8994"

			"qcom,mmsscc-8992"

arch/arm/boot/dts/qcom/msmthorium.dtsi

+91 −2
Original line number Diff line number Diff line
@@ -296,8 +296,27 @@ 
		dma-names = "tx", "rx";

	};



	clock_gcc: qcom,gcc {

		compatible = "qcom,dummycc";

	clock_gcc: qcom,gcc@1800000 {

		compatible = "qcom,gcc-thorium";

		reg = <0x1800000 0x80000>,

			<0xb116000 0x00040>,

			<0xb016000 0x00040>,

			<0xb1d0000 0x00040>;

		reg-names = "cc_base", "apcs_c0_base",

			"apcs_c1_base", "apcs_cci_base";

		vdd_dig-supply = <&pmthorium_s2_level>;

		vdd_sr2_dig-supply = <&pmthorium_s2_level_ao>;

		vdd_sr2_pll-supply = <&pmthorium_l7_ao>;

		vdd_hf_dig-supply = <&pmthorium_s2_level_ao>;

		vdd_hf_pll-supply = <&pmthorium_l7_ao>;

		#clock-cells = <1>;

	};



	clock_debug: qcom,cc-debug@1874000 {

		compatible = "qcom,cc-debug-thorium";

		reg = <0x1874000 0x4>,

		      <0xb11101c 0x8>;

		reg-names = "cc_base", "meas";

		#clock-cells = <1>;

	};
@@ -787,3 +806,73 @@ 
#include "msmthorium-regulator.dtsi"

#include "msm-pmthorium.dtsi"

#include "msm-pmithorium.dtsi"

#include "msm-gdsc-8916.dtsi"



&gdsc_venus {

	clock-names = "bus_clk", "core_clk";

	clocks = <&clock_gcc clk_gcc_venus0_axi_clk>,

		 <&clock_gcc clk_gcc_venus0_vcodec0_clk>;

	status = "okay";

};



&gdsc_venus_core0 {

	qcom,support-hw-trigger;

	clock-names ="core0_clk";

	clocks = <&clock_gcc clk_gcc_venus0_core0_vcodec0_clk>;

	status = "okay";

};



&gdsc_mdss {

	clock-names = "core_clk", "bus_clk";

	clocks = <&clock_gcc clk_gcc_mdss_mdp_clk>,

		 <&clock_gcc clk_gcc_mdss_axi_clk>;

	status = "okay";

};



&gdsc_jpeg {

	clock-names = "core_clk", "bus_clk";

	clocks = <&clock_gcc clk_gcc_camss_jpeg0_clk>,

		 <&clock_gcc clk_gcc_camss_jpeg_axi_clk>;

	status = "okay";

};



&gdsc_vfe {

	clock-names = "core_clk", "bus_clk", "micro_clk",

			"csi_clk";

	clocks = <&clock_gcc clk_gcc_camss_vfe0_clk>,

		 <&clock_gcc clk_gcc_camss_vfe_axi_clk>,

		 <&clock_gcc clk_gcc_camss_micro_ahb_clk>,

		 <&clock_gcc clk_gcc_camss_csi_vfe0_clk>;

	status = "okay";

};



&gdsc_vfe1 {

	clock-names = "core_clk", "bus_clk", "micro_clk",

			"csi_clk";

	clocks = <&clock_gcc clk_gcc_camss_vfe1_clk>,

		 <&clock_gcc clk_gcc_camss_vfe1_axi_clk>,

		 <&clock_gcc clk_gcc_camss_micro_ahb_clk>,

		 <&clock_gcc clk_gcc_camss_csi_vfe1_clk>;

	status = "okay";

};



&gdsc_cpp {

	clock-names = "core_clk", "bus_clk";

	clocks = <&clock_gcc clk_gcc_camss_cpp_clk>,

		 <&clock_gcc clk_gcc_camss_cpp_axi_clk>;

	status = "okay";

};



&gdsc_oxili_gx {

	clock-names = "core_root_clk", "gmem_clk";

	clocks =<&clock_gcc clk_gfx3d_clk_src>,

		<&clock_gcc clk_gcc_oxili_gmem_clk>;

	qcom,enable-root-clk;

	qcom,clk-dis-wait-val = <0x5>;

	status = "okay";

};



&gdsc_oxili_cx {

	reg = <0x1859044 0x4>;

	status = "okay";

};

drivers/clk/msm/clock-gcc-8952.c

+622 −134

File changed.

Preview size limit exceeded, changes collapsed.

include/dt-bindings/clock/msm-clocks-8952.h

+14 −0
Original line number Diff line number Diff line
@@ -109,6 +109,7 @@ 
#define clk_gcc_crypto_axi_clk			0xd4415c9b

#define clk_gcc_crypto_clk			0x00d390d2

#define clk_gcc_prng_ahb_clk			0x397e7eaa

#define clk_gcc_qdss_dap_clk			0x7fa9aa73

#define clk_gcc_apss_tcu_clk			0xaf56a329

#define clk_gcc_ipa_tbu_clk			0x75bbfb5c

#define clk_gcc_gfx_tbu_clk			0x18bb9a90
@@ -194,6 +195,7 @@ 
#define clk_gcc_oxili_ahb_clk			0xd15c8a00

#define clk_gcc_oxili_gfx3d_clk			0x49a51fd9

#define clk_gcc_oxili_timer_clk			0x1180db06

#define clk_gcc_oxili_aon_clk			0xae18e54d

#define clk_gcc_pdm2_clk			0x99d55711

#define clk_gcc_pdm_ahb_clk			0x365664f6

#define clk_gcc_sdcc1_ahb_clk			0x691e0caa
@@ -224,6 +226,18 @@ 
#define clk_byte_clk_src                        0x3a911c53

#define clk_ext_pclk0_clk_src			0x087c1612

#define clk_ext_byte0_clk_src			0xfb32f31e



#define clk_ext_pclk1_clk_src			0x8067c5a3

#define clk_ext_byte1_clk_src			0x585ef6d4

#define clk_byte1_clk_src			0x63c2c955

#define clk_esc1_clk_src			0x3b0afa42

#define clk_pclk1_clk_src			0x090f68ac

#define clk_gcc_mdss_pclk1_clk			0x9a9c430d

#define clk_gcc_mdss_byte1_clk			0x41f97fd8

#define clk_gcc_mdss_esc1_clk			0x34653cc7

#define clk_gcc_dcc_clk				0xd1000c50

#define clk_gcc_debug_mux_thorium		0x917968c2



/* clock_rpm controlled clocks */

#define clk_pnoc_clk				0xc1296d0f

#define clk_pnoc_a_clk				0x9bcffee4

include/dt-bindings/clock/msm-clocks-hwio-8952.h

+146 −0
Original line number Diff line number Diff line
@@ -104,6 +104,7 @@ 
#define GFX_TCU_CBCR			0x12020

#define JPEG_TBU_CBCR			0x12034

#define SMMU_CFG_CBCR			0x12038

#define QDSS_DAP_CBCR			0x29084

#define VFE_TBU_CBCR			0x1203C

#define VFE1_TBU_CBCR			0x12090

#define CPP_TBU_CBCR			0x12040
@@ -201,6 +202,7 @@ 
#define OXILI_GMEM_CBCR			0x59024

#define OXILI_AHB_CBCR			0x59028

#define OXILI_TIMER_CBCR		0x59040

#define OXILI_AON_CBCR			0x5904C

#define CAMSS_TOP_AHB_CMD_RCGR		0x5A000

#define BIMC_GPU_CBCR			0x59030

#define GTCU_AHB_CBCR			0x12044
@@ -208,6 +210,14 @@ 
#define SYSTEM_MM_NOC_CMD_RCGR		0x3D000

#define USB_FS_BCR			0x3F000



#define BYTE1_CMD_RCGR			0x4D0B0

#define ESC1_CMD_RCGR			0x4D0A8

#define PCLK1_CMD_RCGR			0x4D0B8

#define MDSS_BYTE1_CBCR			0x4D0A0

#define MDSS_ESC1_CBCR			0x4D09C

#define MDSS_PCLK1_CBCR			0x4D0A4

#define DCC_CBCR			0x77004



#define RPM_MISC_CLK_TYPE		0x306b6c63

#define RPM_BUS_CLK_TYPE		0x316b6c63

#define RPM_MEM_CLK_TYPE		0x326b6c63
@@ -257,4 +267,140 @@ 
#define APCS_C1_PLL_CONFIG_CTL		0x00014

#define APCS_C1_PLL_STATUS		0x0001C





#define CLKFLAG_WAKEUP_CYCLES		0x0

#define CLKFLAG_SLEEP_CYCLES		0x0



/* Mux source select values */

#define xo_source_val			0

#define xo_a_source_val			0

#define gpll0_source_val		1

#define gpll3_source_val		2

#define gpll0_out_main_source_val	1   /* sdcc1_ice_core */

/* cci_clk_src and usb_fs_system_clk_src */

#define gpll0_out_aux_source_val	2

#define gpll4_source_val		2   /* sdcc1_apss_clk_src */

#define gpll6_source_val		2   /* mclk0_2_clk_src */

#define gpll6_aux_source_val		3   /* gfx3d_clk_src */

#define gpll6_out_main_source_val	1   /* usb_fs_ic_clk_src */

#define dsi0_phypll_source_val		1

#define dsi0_0phypll_source_val		1   /* byte0_clk & pclk0_clk */

#define dsi0_1phypll_source_val         3   /* byte1_clk & pclk1_clk */

#define dsi1_0phypll_source_val         3   /* byte0_clk & pclk0_clk */

#define dsi1_1phypll_source_val         1   /* byte1_clk & pclk1_clk */





#define F(f, s, div, m, n) \

	{ \

		.freq_hz = (f), \

		.src_clk = &s##_clk_src.c, \

		.m_val = (m), \

		.n_val = ~((n)-(m)) * !!(n), \

		.d_val = ~(n),\

		.div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \

			| BVAL(10, 8, s##_source_val), \

	}



#define F_SLEW(f, s_f, s, div, m, n) \

	{ \

		.freq_hz = (f), \

		.src_freq = (s_f), \

		.src_clk = &s##_clk_src.c, \

		.m_val = (m), \

		.n_val = ~((n)-(m)) * !!(n), \

		.d_val = ~(n),\

		.div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \

			| BVAL(10, 8, s##_source_val), \

	}



#define F_APCS_PLL(f, l, m, n, pre_div, post_div, vco) \

	{ \

		.freq_hz = (f), \

		.l_val = (l), \

		.m_val = (m), \

		.n_val = (n), \

		.pre_div_val = BVAL(12, 12, (pre_div)), \

		.post_div_val = BVAL(9, 8, (post_div)), \

		.vco_val = BVAL(29, 28, (vco)), \

	}



#define VDD_DIG_FMAX_MAP1(l1, f1) \

	.vdd_class = &vdd_dig, \

	.fmax = (unsigned long[VDD_DIG_NUM]) {  \

		[VDD_DIG_##l1] = (f1),          \

	},                                      \

	.num_fmax = VDD_DIG_NUM



#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \

	.vdd_class = &vdd_dig, \

	.fmax = (unsigned long[VDD_DIG_NUM]) {  \

		[VDD_DIG_##l1] = (f1),          \

		[VDD_DIG_##l2] = (f2),          \

	},                                      \

	.num_fmax = VDD_DIG_NUM



# define OVERRIDE_FMAX2(clkname, l1, f1, l2, f2) \

	clkname##_clk_src.c.fmax[VDD_DIG_##l1] = (f1);  \

	clkname##_clk_src.c.fmax[VDD_DIG_##l2] = (f2)



#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \

	.vdd_class = &vdd_dig, \

	.fmax = (unsigned long[VDD_DIG_NUM]) {  \

		[VDD_DIG_##l1] = (f1),          \

		[VDD_DIG_##l2] = (f2),          \

		[VDD_DIG_##l3] = (f3),          \

	},                                      \

	.num_fmax = VDD_DIG_NUM



# define OVERRIDE_FMAX3(clkname, l1, f1, l2, f2, l3, f3) \

	clkname##_clk_src.c.fmax[VDD_DIG_##l1] = (f1);\

	clkname##_clk_src.c.fmax[VDD_DIG_##l2] = (f2);\

	clkname##_clk_src.c.fmax[VDD_DIG_##l3] = (f3)





# define OVERRIDE_FMAX4(clkname, l1, f1, l2, f2, l3, f3, l4, f4) \

	clkname##_clk_src.c.fmax[VDD_DIG_##l1] = (f1);\

	clkname##_clk_src.c.fmax[VDD_DIG_##l2] = (f2);\

	clkname##_clk_src.c.fmax[VDD_DIG_##l3] = (f3);\

	clkname##_clk_src.c.fmax[VDD_DIG_##l4] = (f4)



#define VDD_DIG_FMAX_MAP5(l1, f1, l2, f2, l3, f3, l4, f4, l5, f5) \

	.vdd_class = &vdd_dig, \

	.fmax = (unsigned long[VDD_DIG_NUM]) {  \

		[VDD_DIG_##l1] = (f1),\

		[VDD_DIG_##l2] = (f2),\

		[VDD_DIG_##l3] = (f3),\

		[VDD_DIG_##l4] = (f4),\

		[VDD_DIG_##l5] = (f5),\

	},\

	.num_fmax = VDD_DIG_NUM



#define OVERRIDE_FMAX5(clkname, l1, f1, l2, f2, l3, f3, l4, f4, l5, f5) \

	clkname##_clk_src.c.fmax[VDD_DIG_##l1] = (f1);\

	clkname##_clk_src.c.fmax[VDD_DIG_##l2] = (f2);\

	clkname##_clk_src.c.fmax[VDD_DIG_##l3] = (f3);\

	clkname##_clk_src.c.fmax[VDD_DIG_##l4] = (f4);\

	clkname##_clk_src.c.fmax[VDD_DIG_##l5] = (f5)



#define OVERRIDE_FTABLE(clkname, ftable) \

	clkname##_clk_src.freq_tbl = ftable##_thorium



enum vdd_dig_levels {

	VDD_DIG_NONE,

	VDD_DIG_LOWER,

	VDD_DIG_LOW,

	VDD_DIG_NOMINAL,

	VDD_DIG_NOM_PLUS,

	VDD_DIG_HIGH,

	VDD_DIG_NUM

};



int vdd_corner[] = {

	RPM_REGULATOR_LEVEL_NONE,		/* VDD_DIG_NONE */

	RPM_REGULATOR_LEVEL_SVS,		/* VDD_DIG_SVS */

	RPM_REGULATOR_LEVEL_SVS_PLUS,		/* VDD_DIG_SVS_PLUS */

	RPM_REGULATOR_LEVEL_NOM,		/* VDD_DIG_NOM */

	RPM_REGULATOR_LEVEL_NOM_PLUS,		/* VDD_DIG_NOM_PLUS */

	RPM_REGULATOR_LEVEL_TURBO,		/* VDD_DIG_TURBO */

};

#endif