Loading Makefile +1 −1 Original line number Diff line number Diff line VERSION = 3 PATCHLEVEL = 18 SUBLEVEL = 27 SUBLEVEL = 28 EXTRAVERSION = NAME = Diseased Newt Loading arch/arm/common/icst.c +7 −2 Original line number Diff line number Diff line Loading @@ -16,7 +16,7 @@ */ #include <linux/module.h> #include <linux/kernel.h> #include <asm/div64.h> #include <asm/hardware/icst.h> /* Loading @@ -29,7 +29,11 @@ EXPORT_SYMBOL(icst525_s2div); unsigned long icst_hz(const struct icst_params *p, struct icst_vco vco) { return p->ref * 2 * (vco.v + 8) / ((vco.r + 2) * p->s2div[vco.s]); u64 dividend = p->ref * 2 * (u64)(vco.v + 8); u32 divisor = (vco.r + 2) * p->s2div[vco.s]; do_div(dividend, divisor); return (unsigned long)dividend; } EXPORT_SYMBOL(icst_hz); Loading Loading @@ -58,6 +62,7 @@ icst_hz_to_vco(const struct icst_params *p, unsigned long freq) if (f > p->vco_min && f <= p->vco_max) break; i++; } while (i < 8); if (i >= 8) Loading arch/mips/include/asm/syscall.h +1 −3 Original line number Diff line number Diff line Loading @@ -107,10 +107,8 @@ static inline void syscall_get_arguments(struct task_struct *task, /* O32 ABI syscall() - Either 64-bit with O32 or 32-bit */ if ((config_enabled(CONFIG_32BIT) || test_tsk_thread_flag(task, TIF_32BIT_REGS)) && (regs->regs[2] == __NR_syscall)) { (regs->regs[2] == __NR_syscall)) i++; n++; } while (n--) ret |= mips_get_syscall_arg(args++, task, regs, i++); Loading arch/powerpc/platforms/powernv/eeh-powernv.c +52 −52 Original line number Diff line number Diff line Loading @@ -39,11 +39,11 @@ #include "pci.h" /** * powernv_eeh_init - EEH platform dependent initialization * pnv_eeh_init - EEH platform dependent initialization * * EEH platform dependent initialization on powernv */ static int powernv_eeh_init(void) static int pnv_eeh_init(void) { struct pci_controller *hose; struct pnv_phb *phb; Loading Loading @@ -75,14 +75,14 @@ static int powernv_eeh_init(void) } /** * powernv_eeh_post_init - EEH platform dependent post initialization * pnv_eeh_post_init - EEH platform dependent post initialization * * EEH platform dependent post initialization on powernv. When * the function is called, the EEH PEs and devices should have * been built. If the I/O cache staff has been built, EEH is * ready to supply service. */ static int powernv_eeh_post_init(void) static int pnv_eeh_post_init(void) { struct pci_controller *hose; struct pnv_phb *phb; Loading @@ -102,7 +102,7 @@ static int powernv_eeh_post_init(void) } /** * powernv_eeh_dev_probe - Do probe on PCI device * pnv_eeh_dev_probe - Do probe on PCI device * @dev: PCI device * @flag: unused * Loading @@ -118,7 +118,7 @@ static int powernv_eeh_post_init(void) * was possiblly triggered by EEH core, the binding between EEH device * and the PCI device isn't built yet. */ static int powernv_eeh_dev_probe(struct pci_dev *dev, void *flag) static int pnv_eeh_dev_probe(struct pci_dev *dev, void *flag) { struct pci_controller *hose = pci_bus_to_host(dev->bus); struct pnv_phb *phb = hose->private_data; Loading Loading @@ -210,7 +210,7 @@ static int powernv_eeh_dev_probe(struct pci_dev *dev, void *flag) } /** * powernv_eeh_set_option - Initialize EEH or MMIO/DMA reenable * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable * @pe: EEH PE * @option: operation to be issued * Loading @@ -218,7 +218,7 @@ static int powernv_eeh_dev_probe(struct pci_dev *dev, void *flag) * Currently, following options are support according to PAPR: * Enable EEH, Disable EEH, Enable MMIO and Enable DMA */ static int powernv_eeh_set_option(struct eeh_pe *pe, int option) static int pnv_eeh_set_option(struct eeh_pe *pe, int option) { struct pci_controller *hose = pe->phb; struct pnv_phb *phb = hose->private_data; Loading @@ -235,19 +235,19 @@ static int powernv_eeh_set_option(struct eeh_pe *pe, int option) } /** * powernv_eeh_get_pe_addr - Retrieve PE address * pnv_eeh_get_pe_addr - Retrieve PE address * @pe: EEH PE * * Retrieve the PE address according to the given tranditional * PCI BDF (Bus/Device/Function) address. */ static int powernv_eeh_get_pe_addr(struct eeh_pe *pe) static int pnv_eeh_get_pe_addr(struct eeh_pe *pe) { return pe->addr; } /** * powernv_eeh_get_state - Retrieve PE state * pnv_eeh_get_state - Retrieve PE state * @pe: EEH PE * @delay: delay while PE state is temporarily unavailable * Loading @@ -256,7 +256,7 @@ static int powernv_eeh_get_pe_addr(struct eeh_pe *pe) * we prefer passing down to hardware implementation to handle * it. */ static int powernv_eeh_get_state(struct eeh_pe *pe, int *delay) static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay) { struct pci_controller *hose = pe->phb; struct pnv_phb *phb = hose->private_data; Loading @@ -281,13 +281,13 @@ static int powernv_eeh_get_state(struct eeh_pe *pe, int *delay) } /** * powernv_eeh_reset - Reset the specified PE * pnv_eeh_reset - Reset the specified PE * @pe: EEH PE * @option: reset option * * Reset the specified PE */ static int powernv_eeh_reset(struct eeh_pe *pe, int option) static int pnv_eeh_reset(struct eeh_pe *pe, int option) { struct pci_controller *hose = pe->phb; struct pnv_phb *phb = hose->private_data; Loading @@ -300,20 +300,20 @@ static int powernv_eeh_reset(struct eeh_pe *pe, int option) } /** * powernv_eeh_wait_state - Wait for PE state * pnv_eeh_wait_state - Wait for PE state * @pe: EEH PE * @max_wait: maximal period in microsecond * * Wait for the state of associated PE. It might take some time * to retrieve the PE's state. */ static int powernv_eeh_wait_state(struct eeh_pe *pe, int max_wait) static int pnv_eeh_wait_state(struct eeh_pe *pe, int max_wait) { int ret; int mwait; while (1) { ret = powernv_eeh_get_state(pe, &mwait); ret = pnv_eeh_get_state(pe, &mwait); /* * If the PE's state is temporarily unavailable, Loading @@ -337,7 +337,7 @@ static int powernv_eeh_wait_state(struct eeh_pe *pe, int max_wait) } /** * powernv_eeh_get_log - Retrieve error log * pnv_eeh_get_log - Retrieve error log * @pe: EEH PE * @severity: temporary or permanent error log * @drv_log: driver log to be combined with retrieved error log Loading @@ -345,7 +345,7 @@ static int powernv_eeh_wait_state(struct eeh_pe *pe, int max_wait) * * Retrieve the temporary or permanent error from the PE. */ static int powernv_eeh_get_log(struct eeh_pe *pe, int severity, static int pnv_eeh_get_log(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len) { struct pci_controller *hose = pe->phb; Loading @@ -359,14 +359,14 @@ static int powernv_eeh_get_log(struct eeh_pe *pe, int severity, } /** * powernv_eeh_configure_bridge - Configure PCI bridges in the indicated PE * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE * @pe: EEH PE * * The function will be called to reconfigure the bridges included * in the specified PE so that the mulfunctional PE would be recovered * again. */ static int powernv_eeh_configure_bridge(struct eeh_pe *pe) static int pnv_eeh_configure_bridge(struct eeh_pe *pe) { struct pci_controller *hose = pe->phb; struct pnv_phb *phb = hose->private_data; Loading @@ -379,7 +379,7 @@ static int powernv_eeh_configure_bridge(struct eeh_pe *pe) } /** * powernv_pe_err_inject - Inject specified error to the indicated PE * pnv_pe_err_inject - Inject specified error to the indicated PE * @pe: the indicated PE * @type: error type * @func: specific error type Loading @@ -390,7 +390,7 @@ static int powernv_eeh_configure_bridge(struct eeh_pe *pe) * determined by @type and @func, to the indicated PE for * testing purpose. */ static int powernv_eeh_err_inject(struct eeh_pe *pe, int type, int func, static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func, unsigned long addr, unsigned long mask) { struct pci_controller *hose = pe->phb; Loading @@ -403,7 +403,7 @@ static int powernv_eeh_err_inject(struct eeh_pe *pe, int type, int func, return ret; } static inline bool powernv_eeh_cfg_blocked(struct device_node *dn) static inline bool pnv_eeh_cfg_blocked(struct device_node *dn) { struct eeh_dev *edev = of_node_to_eeh_dev(dn); Loading @@ -416,10 +416,10 @@ static inline bool powernv_eeh_cfg_blocked(struct device_node *dn) return false; } static int powernv_eeh_read_config(struct device_node *dn, static int pnv_eeh_read_config(struct device_node *dn, int where, int size, u32 *val) { if (powernv_eeh_cfg_blocked(dn)) { if (pnv_eeh_cfg_blocked(dn)) { *val = 0xFFFFFFFF; return PCIBIOS_SET_FAILED; } Loading @@ -427,22 +427,22 @@ static int powernv_eeh_read_config(struct device_node *dn, return pnv_pci_cfg_read(dn, where, size, val); } static int powernv_eeh_write_config(struct device_node *dn, static int pnv_eeh_write_config(struct device_node *dn, int where, int size, u32 val) { if (powernv_eeh_cfg_blocked(dn)) if (pnv_eeh_cfg_blocked(dn)) return PCIBIOS_SET_FAILED; return pnv_pci_cfg_write(dn, where, size, val); } /** * powernv_eeh_next_error - Retrieve next EEH error to handle * pnv_eeh_next_error - Retrieve next EEH error to handle * @pe: Affected PE * * Using OPAL API, to retrieve next EEH error for EEH core to handle */ static int powernv_eeh_next_error(struct eeh_pe **pe) static int pnv_eeh_next_error(struct eeh_pe **pe) { struct pci_controller *hose; struct pnv_phb *phb = NULL; Loading @@ -458,7 +458,7 @@ static int powernv_eeh_next_error(struct eeh_pe **pe) return -EEXIST; } static int powernv_eeh_restore_config(struct device_node *dn) static int pnv_eeh_restore_config(struct device_node *dn) { struct eeh_dev *edev = of_node_to_eeh_dev(dn); struct pnv_phb *phb; Loading @@ -479,24 +479,24 @@ static int powernv_eeh_restore_config(struct device_node *dn) return 0; } static struct eeh_ops powernv_eeh_ops = { static struct eeh_ops pnv_eeh_ops = { .name = "powernv", .init = powernv_eeh_init, .post_init = powernv_eeh_post_init, .init = pnv_eeh_init, .post_init = pnv_eeh_post_init, .of_probe = NULL, .dev_probe = powernv_eeh_dev_probe, .set_option = powernv_eeh_set_option, .get_pe_addr = powernv_eeh_get_pe_addr, .get_state = powernv_eeh_get_state, .reset = powernv_eeh_reset, .wait_state = powernv_eeh_wait_state, .get_log = powernv_eeh_get_log, .configure_bridge = powernv_eeh_configure_bridge, .err_inject = powernv_eeh_err_inject, .read_config = powernv_eeh_read_config, .write_config = powernv_eeh_write_config, .next_error = powernv_eeh_next_error, .restore_config = powernv_eeh_restore_config .dev_probe = pnv_eeh_dev_probe, .set_option = pnv_eeh_set_option, .get_pe_addr = pnv_eeh_get_pe_addr, .get_state = pnv_eeh_get_state, .reset = pnv_eeh_reset, .wait_state = pnv_eeh_wait_state, .get_log = pnv_eeh_get_log, .configure_bridge = pnv_eeh_configure_bridge, .err_inject = pnv_eeh_err_inject, .read_config = pnv_eeh_read_config, .write_config = pnv_eeh_write_config, .next_error = pnv_eeh_next_error, .restore_config = pnv_eeh_restore_config }; /** Loading @@ -510,7 +510,7 @@ static int __init eeh_powernv_init(void) int ret = -EINVAL; eeh_set_pe_aux_size(PNV_PCI_DIAG_BUF_SIZE); ret = eeh_ops_register(&powernv_eeh_ops); ret = eeh_ops_register(&pnv_eeh_ops); if (!ret) pr_info("EEH: PowerNV platform initialized\n"); else Loading crypto/crypto_user.c +5 −1 Original line number Diff line number Diff line Loading @@ -483,6 +483,7 @@ static int crypto_user_rcv_msg(struct sk_buff *skb, struct nlmsghdr *nlh) if (link->dump == NULL) return -EINVAL; down_read(&crypto_alg_sem); list_for_each_entry(alg, &crypto_alg_list, cra_list) dump_alloc += CRYPTO_REPORT_MAXSIZE; Loading @@ -492,8 +493,11 @@ static int crypto_user_rcv_msg(struct sk_buff *skb, struct nlmsghdr *nlh) .done = link->done, .min_dump_alloc = dump_alloc, }; return netlink_dump_start(crypto_nlsk, skb, nlh, &c); err = netlink_dump_start(crypto_nlsk, skb, nlh, &c); } up_read(&crypto_alg_sem); return err; } err = nlmsg_parse(nlh, crypto_msg_min[type], attrs, CRYPTOCFGA_MAX, Loading Loading
Makefile +1 −1 Original line number Diff line number Diff line VERSION = 3 PATCHLEVEL = 18 SUBLEVEL = 27 SUBLEVEL = 28 EXTRAVERSION = NAME = Diseased Newt Loading
arch/arm/common/icst.c +7 −2 Original line number Diff line number Diff line Loading @@ -16,7 +16,7 @@ */ #include <linux/module.h> #include <linux/kernel.h> #include <asm/div64.h> #include <asm/hardware/icst.h> /* Loading @@ -29,7 +29,11 @@ EXPORT_SYMBOL(icst525_s2div); unsigned long icst_hz(const struct icst_params *p, struct icst_vco vco) { return p->ref * 2 * (vco.v + 8) / ((vco.r + 2) * p->s2div[vco.s]); u64 dividend = p->ref * 2 * (u64)(vco.v + 8); u32 divisor = (vco.r + 2) * p->s2div[vco.s]; do_div(dividend, divisor); return (unsigned long)dividend; } EXPORT_SYMBOL(icst_hz); Loading Loading @@ -58,6 +62,7 @@ icst_hz_to_vco(const struct icst_params *p, unsigned long freq) if (f > p->vco_min && f <= p->vco_max) break; i++; } while (i < 8); if (i >= 8) Loading
arch/mips/include/asm/syscall.h +1 −3 Original line number Diff line number Diff line Loading @@ -107,10 +107,8 @@ static inline void syscall_get_arguments(struct task_struct *task, /* O32 ABI syscall() - Either 64-bit with O32 or 32-bit */ if ((config_enabled(CONFIG_32BIT) || test_tsk_thread_flag(task, TIF_32BIT_REGS)) && (regs->regs[2] == __NR_syscall)) { (regs->regs[2] == __NR_syscall)) i++; n++; } while (n--) ret |= mips_get_syscall_arg(args++, task, regs, i++); Loading
arch/powerpc/platforms/powernv/eeh-powernv.c +52 −52 Original line number Diff line number Diff line Loading @@ -39,11 +39,11 @@ #include "pci.h" /** * powernv_eeh_init - EEH platform dependent initialization * pnv_eeh_init - EEH platform dependent initialization * * EEH platform dependent initialization on powernv */ static int powernv_eeh_init(void) static int pnv_eeh_init(void) { struct pci_controller *hose; struct pnv_phb *phb; Loading Loading @@ -75,14 +75,14 @@ static int powernv_eeh_init(void) } /** * powernv_eeh_post_init - EEH platform dependent post initialization * pnv_eeh_post_init - EEH platform dependent post initialization * * EEH platform dependent post initialization on powernv. When * the function is called, the EEH PEs and devices should have * been built. If the I/O cache staff has been built, EEH is * ready to supply service. */ static int powernv_eeh_post_init(void) static int pnv_eeh_post_init(void) { struct pci_controller *hose; struct pnv_phb *phb; Loading @@ -102,7 +102,7 @@ static int powernv_eeh_post_init(void) } /** * powernv_eeh_dev_probe - Do probe on PCI device * pnv_eeh_dev_probe - Do probe on PCI device * @dev: PCI device * @flag: unused * Loading @@ -118,7 +118,7 @@ static int powernv_eeh_post_init(void) * was possiblly triggered by EEH core, the binding between EEH device * and the PCI device isn't built yet. */ static int powernv_eeh_dev_probe(struct pci_dev *dev, void *flag) static int pnv_eeh_dev_probe(struct pci_dev *dev, void *flag) { struct pci_controller *hose = pci_bus_to_host(dev->bus); struct pnv_phb *phb = hose->private_data; Loading Loading @@ -210,7 +210,7 @@ static int powernv_eeh_dev_probe(struct pci_dev *dev, void *flag) } /** * powernv_eeh_set_option - Initialize EEH or MMIO/DMA reenable * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable * @pe: EEH PE * @option: operation to be issued * Loading @@ -218,7 +218,7 @@ static int powernv_eeh_dev_probe(struct pci_dev *dev, void *flag) * Currently, following options are support according to PAPR: * Enable EEH, Disable EEH, Enable MMIO and Enable DMA */ static int powernv_eeh_set_option(struct eeh_pe *pe, int option) static int pnv_eeh_set_option(struct eeh_pe *pe, int option) { struct pci_controller *hose = pe->phb; struct pnv_phb *phb = hose->private_data; Loading @@ -235,19 +235,19 @@ static int powernv_eeh_set_option(struct eeh_pe *pe, int option) } /** * powernv_eeh_get_pe_addr - Retrieve PE address * pnv_eeh_get_pe_addr - Retrieve PE address * @pe: EEH PE * * Retrieve the PE address according to the given tranditional * PCI BDF (Bus/Device/Function) address. */ static int powernv_eeh_get_pe_addr(struct eeh_pe *pe) static int pnv_eeh_get_pe_addr(struct eeh_pe *pe) { return pe->addr; } /** * powernv_eeh_get_state - Retrieve PE state * pnv_eeh_get_state - Retrieve PE state * @pe: EEH PE * @delay: delay while PE state is temporarily unavailable * Loading @@ -256,7 +256,7 @@ static int powernv_eeh_get_pe_addr(struct eeh_pe *pe) * we prefer passing down to hardware implementation to handle * it. */ static int powernv_eeh_get_state(struct eeh_pe *pe, int *delay) static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay) { struct pci_controller *hose = pe->phb; struct pnv_phb *phb = hose->private_data; Loading @@ -281,13 +281,13 @@ static int powernv_eeh_get_state(struct eeh_pe *pe, int *delay) } /** * powernv_eeh_reset - Reset the specified PE * pnv_eeh_reset - Reset the specified PE * @pe: EEH PE * @option: reset option * * Reset the specified PE */ static int powernv_eeh_reset(struct eeh_pe *pe, int option) static int pnv_eeh_reset(struct eeh_pe *pe, int option) { struct pci_controller *hose = pe->phb; struct pnv_phb *phb = hose->private_data; Loading @@ -300,20 +300,20 @@ static int powernv_eeh_reset(struct eeh_pe *pe, int option) } /** * powernv_eeh_wait_state - Wait for PE state * pnv_eeh_wait_state - Wait for PE state * @pe: EEH PE * @max_wait: maximal period in microsecond * * Wait for the state of associated PE. It might take some time * to retrieve the PE's state. */ static int powernv_eeh_wait_state(struct eeh_pe *pe, int max_wait) static int pnv_eeh_wait_state(struct eeh_pe *pe, int max_wait) { int ret; int mwait; while (1) { ret = powernv_eeh_get_state(pe, &mwait); ret = pnv_eeh_get_state(pe, &mwait); /* * If the PE's state is temporarily unavailable, Loading @@ -337,7 +337,7 @@ static int powernv_eeh_wait_state(struct eeh_pe *pe, int max_wait) } /** * powernv_eeh_get_log - Retrieve error log * pnv_eeh_get_log - Retrieve error log * @pe: EEH PE * @severity: temporary or permanent error log * @drv_log: driver log to be combined with retrieved error log Loading @@ -345,7 +345,7 @@ static int powernv_eeh_wait_state(struct eeh_pe *pe, int max_wait) * * Retrieve the temporary or permanent error from the PE. */ static int powernv_eeh_get_log(struct eeh_pe *pe, int severity, static int pnv_eeh_get_log(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len) { struct pci_controller *hose = pe->phb; Loading @@ -359,14 +359,14 @@ static int powernv_eeh_get_log(struct eeh_pe *pe, int severity, } /** * powernv_eeh_configure_bridge - Configure PCI bridges in the indicated PE * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE * @pe: EEH PE * * The function will be called to reconfigure the bridges included * in the specified PE so that the mulfunctional PE would be recovered * again. */ static int powernv_eeh_configure_bridge(struct eeh_pe *pe) static int pnv_eeh_configure_bridge(struct eeh_pe *pe) { struct pci_controller *hose = pe->phb; struct pnv_phb *phb = hose->private_data; Loading @@ -379,7 +379,7 @@ static int powernv_eeh_configure_bridge(struct eeh_pe *pe) } /** * powernv_pe_err_inject - Inject specified error to the indicated PE * pnv_pe_err_inject - Inject specified error to the indicated PE * @pe: the indicated PE * @type: error type * @func: specific error type Loading @@ -390,7 +390,7 @@ static int powernv_eeh_configure_bridge(struct eeh_pe *pe) * determined by @type and @func, to the indicated PE for * testing purpose. */ static int powernv_eeh_err_inject(struct eeh_pe *pe, int type, int func, static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func, unsigned long addr, unsigned long mask) { struct pci_controller *hose = pe->phb; Loading @@ -403,7 +403,7 @@ static int powernv_eeh_err_inject(struct eeh_pe *pe, int type, int func, return ret; } static inline bool powernv_eeh_cfg_blocked(struct device_node *dn) static inline bool pnv_eeh_cfg_blocked(struct device_node *dn) { struct eeh_dev *edev = of_node_to_eeh_dev(dn); Loading @@ -416,10 +416,10 @@ static inline bool powernv_eeh_cfg_blocked(struct device_node *dn) return false; } static int powernv_eeh_read_config(struct device_node *dn, static int pnv_eeh_read_config(struct device_node *dn, int where, int size, u32 *val) { if (powernv_eeh_cfg_blocked(dn)) { if (pnv_eeh_cfg_blocked(dn)) { *val = 0xFFFFFFFF; return PCIBIOS_SET_FAILED; } Loading @@ -427,22 +427,22 @@ static int powernv_eeh_read_config(struct device_node *dn, return pnv_pci_cfg_read(dn, where, size, val); } static int powernv_eeh_write_config(struct device_node *dn, static int pnv_eeh_write_config(struct device_node *dn, int where, int size, u32 val) { if (powernv_eeh_cfg_blocked(dn)) if (pnv_eeh_cfg_blocked(dn)) return PCIBIOS_SET_FAILED; return pnv_pci_cfg_write(dn, where, size, val); } /** * powernv_eeh_next_error - Retrieve next EEH error to handle * pnv_eeh_next_error - Retrieve next EEH error to handle * @pe: Affected PE * * Using OPAL API, to retrieve next EEH error for EEH core to handle */ static int powernv_eeh_next_error(struct eeh_pe **pe) static int pnv_eeh_next_error(struct eeh_pe **pe) { struct pci_controller *hose; struct pnv_phb *phb = NULL; Loading @@ -458,7 +458,7 @@ static int powernv_eeh_next_error(struct eeh_pe **pe) return -EEXIST; } static int powernv_eeh_restore_config(struct device_node *dn) static int pnv_eeh_restore_config(struct device_node *dn) { struct eeh_dev *edev = of_node_to_eeh_dev(dn); struct pnv_phb *phb; Loading @@ -479,24 +479,24 @@ static int powernv_eeh_restore_config(struct device_node *dn) return 0; } static struct eeh_ops powernv_eeh_ops = { static struct eeh_ops pnv_eeh_ops = { .name = "powernv", .init = powernv_eeh_init, .post_init = powernv_eeh_post_init, .init = pnv_eeh_init, .post_init = pnv_eeh_post_init, .of_probe = NULL, .dev_probe = powernv_eeh_dev_probe, .set_option = powernv_eeh_set_option, .get_pe_addr = powernv_eeh_get_pe_addr, .get_state = powernv_eeh_get_state, .reset = powernv_eeh_reset, .wait_state = powernv_eeh_wait_state, .get_log = powernv_eeh_get_log, .configure_bridge = powernv_eeh_configure_bridge, .err_inject = powernv_eeh_err_inject, .read_config = powernv_eeh_read_config, .write_config = powernv_eeh_write_config, .next_error = powernv_eeh_next_error, .restore_config = powernv_eeh_restore_config .dev_probe = pnv_eeh_dev_probe, .set_option = pnv_eeh_set_option, .get_pe_addr = pnv_eeh_get_pe_addr, .get_state = pnv_eeh_get_state, .reset = pnv_eeh_reset, .wait_state = pnv_eeh_wait_state, .get_log = pnv_eeh_get_log, .configure_bridge = pnv_eeh_configure_bridge, .err_inject = pnv_eeh_err_inject, .read_config = pnv_eeh_read_config, .write_config = pnv_eeh_write_config, .next_error = pnv_eeh_next_error, .restore_config = pnv_eeh_restore_config }; /** Loading @@ -510,7 +510,7 @@ static int __init eeh_powernv_init(void) int ret = -EINVAL; eeh_set_pe_aux_size(PNV_PCI_DIAG_BUF_SIZE); ret = eeh_ops_register(&powernv_eeh_ops); ret = eeh_ops_register(&pnv_eeh_ops); if (!ret) pr_info("EEH: PowerNV platform initialized\n"); else Loading
crypto/crypto_user.c +5 −1 Original line number Diff line number Diff line Loading @@ -483,6 +483,7 @@ static int crypto_user_rcv_msg(struct sk_buff *skb, struct nlmsghdr *nlh) if (link->dump == NULL) return -EINVAL; down_read(&crypto_alg_sem); list_for_each_entry(alg, &crypto_alg_list, cra_list) dump_alloc += CRYPTO_REPORT_MAXSIZE; Loading @@ -492,8 +493,11 @@ static int crypto_user_rcv_msg(struct sk_buff *skb, struct nlmsghdr *nlh) .done = link->done, .min_dump_alloc = dump_alloc, }; return netlink_dump_start(crypto_nlsk, skb, nlh, &c); err = netlink_dump_start(crypto_nlsk, skb, nlh, &c); } up_read(&crypto_alg_sem); return err; } err = nlmsg_parse(nlh, crypto_msg_min[type], attrs, CRYPTOCFGA_MAX, Loading