Loading arch/arm/boot/dts/qcom/msmcobalt-rumi.dtsi +21 −0 Original line number Original line Diff line number Diff line Loading @@ -45,3 +45,24 @@ status = "ok"; status = "ok"; }; }; &soc { qcom,icnss@18800000 { compatible = "qcom,icnss"; reg = <0x18800000 0x800000>; reg-names = "membase"; interrupts = <0 445 0 /* CE0 */ >, <0 446 0 /* CE1 */ >, <0 447 0 /* CE2 */ >, <0 448 0 /* CE3 */ >, <0 449 0 /* CE4 */ >, <0 450 0 /* CE5 */ >, <0 452 0 /* CE6 */ >, <0 453 0 /* CE7 */ >, <0 454 0 /* CE8 */ >, <0 455 0 /* CE9 */ >, <0 456 0 /* CE10 */ >, <0 457 0 /* CE11 */ >; }; }; Loading
arch/arm/boot/dts/qcom/msmcobalt-rumi.dtsi +21 −0 Original line number Original line Diff line number Diff line Loading @@ -45,3 +45,24 @@ status = "ok"; status = "ok"; }; }; &soc { qcom,icnss@18800000 { compatible = "qcom,icnss"; reg = <0x18800000 0x800000>; reg-names = "membase"; interrupts = <0 445 0 /* CE0 */ >, <0 446 0 /* CE1 */ >, <0 447 0 /* CE2 */ >, <0 448 0 /* CE3 */ >, <0 449 0 /* CE4 */ >, <0 450 0 /* CE5 */ >, <0 452 0 /* CE6 */ >, <0 453 0 /* CE7 */ >, <0 454 0 /* CE8 */ >, <0 455 0 /* CE9 */ >, <0 456 0 /* CE10 */ >, <0 457 0 /* CE11 */ >; }; };