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Commit 813bde43 authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
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drm/i915: don't write powered down IRQ registers on Gen 8 



If we enable unclaimed register reporting on Gen 8, we will discover
that the IRQ registers for pipes B and C are also on the power well,
so writes to them when the power well is disabled result in unclaimed
register errors.

Also, hsw_power_well_post_enable() already takes care of re-enabling
them once the power well is enabled.

Testcase: igt/pm_rpm/rte
Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 480c8033

drivers/gpu/drm/i915/i915_irq.c

+8 −3
Original line number Diff line number Diff line
@@ -3467,6 +3467,8 @@ static void gen8_irq_reset(struct drm_device *dev) 
	gen8_gt_irq_reset(dev_priv);



	for_each_pipe(pipe)

		if (intel_display_power_enabled(dev_priv,

						POWER_DOMAIN_PIPE(pipe)))

			GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);



	GEN5_IRQ_RESET(GEN8_DE_PORT_);
@@ -3800,7 +3802,10 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) 
	dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;



	for_each_pipe(pipe)

		GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, dev_priv->de_irq_mask[pipe],

		if (intel_display_power_enabled(dev_priv,

				POWER_DOMAIN_PIPE(pipe)))

			GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,

					  dev_priv->de_irq_mask[pipe],

					  de_pipe_enables);



	GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A);