Merge "clk: msm: clock-gcc-8952: Modify clock ops for byte & pixel clock" (81347633) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/clk/msm/clock-gcc-8952.c

+49 −23

Original line number	Diff line number	Diff line
		@@ -418,6 +418,8 @@ static struct pll_vote_clk gpll0_clk_src = {

		DEFINE_EXT_CLK(gpll0_out_aux_clk_src, &gpll0_clk_src.c);
		DEFINE_EXT_CLK(gpll0_out_main_clk_src, &gpll0_clk_src.c);
		DEFINE_EXT_CLK(ext_pclk0_clk_src, NULL);
		DEFINE_EXT_CLK(ext_byte0_clk_src, NULL);

		/* Don't vote for xo if using this clock to allow xo shutdown */
		static struct pll_vote_clk gpll0_ao_clk_src = {
		@@ -1292,16 +1294,25 @@ static struct rcg_clk gp3_clk_src = {
		};

		static struct clk_freq_tbl ftbl_gcc_mdss_byte0_clk[] = {
		F_MM(dsi0_phypll),
		{
		.div_src_val = BVAL(10, 8, dsi0_phypll_source_val)
		\| BVAL(4, 0, 0),
		.src_clk = &ext_byte0_clk_src.c,
		.freq_hz = 0,
		},
		F_END
		};

		static struct rcg_clk byte0_clk_src = {
		.cmd_rcgr_reg = BYTE0_CMD_RCGR,
		.set_rate = set_rate_hid,
		.current_freq = ftbl_gcc_mdss_byte0_clk,
		.freq_tbl = ftbl_gcc_mdss_byte0_clk,
		.base = &virt_bases[GCC_BASE],
		.c = {
		.dbg_name = "byte0_clk_src",
		.ops = &clk_ops_byte,
		.ops = &clk_ops_pixel_multiparent,
		.flags = CLKFLAG_NO_RATE_CACHE,
		VDD_DIG_FMAX_MAP2(LOWER, 120000000, NOMINAL, 187500000),
		CLK_INIT(byte0_clk_src.c),
		},
		@@ -1355,17 +1366,26 @@ static struct rcg_clk mdp_clk_src = {
		};

		static struct clk_freq_tbl ftbl_gcc_mdss_pclk0_clk[] = {
		F_MM(dsi0_phypll)
		{
		.div_src_val = BVAL(10, 8, dsi0_phypll_source_val)
		\| BVAL(4, 0, 0),
		.src_clk = &ext_pclk0_clk_src.c,
		.freq_hz = 0,
		},
		F_END
		};

		static struct rcg_clk pclk0_clk_src = {
		.cmd_rcgr_reg = PCLK0_CMD_RCGR,
		.set_rate = set_rate_mnd,
		.current_freq = ftbl_gcc_mdss_pclk0_clk,
		.freq_tbl = ftbl_gcc_mdss_pclk0_clk,
		.base = &virt_bases[GCC_BASE],
		.c = {
		.dbg_name = "pclk0_clk_src",
		.ops = &clk_ops_pixel,
		.ops = &clk_ops_pixel_multiparent,
		VDD_DIG_FMAX_MAP2(LOWER, 160000000, NOMINAL, 250000000),
		.flags = CLKFLAG_NO_RATE_CACHE,
		CLK_INIT(pclk0_clk_src.c),
		},
		};
		@@ -2446,6 +2466,7 @@ static struct branch_clk gcc_mdss_byte0_clk = {
		.dbg_name = "gcc_mdss_byte0_clk",
		.parent = &byte0_clk_src.c,
		.ops = &clk_ops_branch,
		.flags = CLKFLAG_NO_RATE_CACHE,
		CLK_INIT(gcc_mdss_byte0_clk.c),
		},
		};
		@@ -2482,6 +2503,7 @@ static struct branch_clk gcc_mdss_pclk0_clk = {
		.dbg_name = "gcc_mdss_pclk0_clk",
		.parent = &pclk0_clk_src.c,
		.ops = &clk_ops_branch,
		.flags = CLKFLAG_NO_RATE_CACHE,
		CLK_INIT(gcc_mdss_pclk0_clk.c),
		},
		};
		@@ -3739,6 +3761,8 @@ static int __init msm_clock_debug_init(void)

		/* MDSS DSI_PHY_PLL */
		static struct clk_lookup msm_clocks_gcc_mdss[] = {
		CLK_LIST(ext_pclk0_clk_src),
		CLK_LIST(ext_byte0_clk_src),
		CLK_LIST(byte0_clk_src),
		CLK_LIST(pclk0_clk_src),
		CLK_LIST(gcc_mdss_pclk0_clk),
		@@ -3747,38 +3771,40 @@ static struct clk_lookup msm_clocks_gcc_mdss[] = {

		static int msm_gcc_mdss_probe(struct platform_device *pdev)
		{
		int counter, ret;
		int ret = 0;
		struct clk *curr_p;

		pclk0_clk_src.c.parent = devm_clk_get(&pdev->dev, "pixel_src");
		if (IS_ERR(pclk0_clk_src.c.parent)) {
		curr_p = ext_pclk0_clk_src.c.parent = devm_clk_get(&pdev->dev,
		"pixel_src");
		if (IS_ERR(curr_p)) {
		dev_err(&pdev->dev, "Failed to get pixel source.\n");
		return PTR_ERR(pclk0_clk_src.c.parent);
		return PTR_ERR(curr_p);
		}

		for (counter = 0; counter < (sizeof(ftbl_gcc_mdss_pclk0_clk)/
		sizeof(struct clk_freq_tbl)); counter++)
		ftbl_gcc_mdss_pclk0_clk[counter].src_clk =
		pclk0_clk_src.c.parent;

		byte0_clk_src.c.parent = devm_clk_get(&pdev->dev, "byte_src");
		if (IS_ERR(byte0_clk_src.c.parent)) {
		dev_err(&pdev->dev, "Failed to get byte0 source.\n");
		devm_clk_put(&pdev->dev, pclk0_clk_src.c.parent);
		return PTR_ERR(byte0_clk_src.c.parent);
		curr_p = ext_byte0_clk_src.c.parent = devm_clk_get(&pdev->dev,
		"byte_src");
		if (IS_ERR(curr_p)) {
		dev_err(&pdev->dev, "Failed to get byte source.\n");
		ret = PTR_ERR(curr_p);
		goto byte0_fail;
		}

		for (counter = 0; counter < (sizeof(ftbl_gcc_mdss_byte0_clk)/
		sizeof(struct clk_freq_tbl)); counter++)
		ftbl_gcc_mdss_byte0_clk[counter].src_clk =
		byte0_clk_src.c.parent;
		ext_pclk0_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
		ext_byte0_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;


		ret = of_msm_clock_register(pdev->dev.of_node, msm_clocks_gcc_mdss,
		ARRAY_SIZE(msm_clocks_gcc_mdss));
		if (ret)
		return ret;
		goto fail;

		dev_info(&pdev->dev, "Registered GCC MDSS clocks.\n");

		return ret;
		fail:
		devm_clk_put(&pdev->dev, ext_byte0_clk_src.c.parent);
		byte0_fail:
		devm_clk_put(&pdev->dev, ext_pclk0_clk_src.c.parent);
		return ret;
		}

include/dt-bindings/clock/msm-clocks-8952.h

+2 −1

Original line number	Diff line number	Diff line
		@@ -222,7 +222,8 @@

		#define clk_pixel_clk_src 0x8b6f83d8
		#define clk_byte_clk_src 0x3a911c53

		#define clk_ext_pclk0_clk_src 0x087c1612
		#define clk_ext_byte0_clk_src 0xfb32f31e
		/* clock_rpm controlled clocks */
		#define clk_pnoc_clk 0xc1296d0f
		#define clk_pnoc_a_clk 0x9bcffee4