Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 80e829fa authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: implement ColorBlt w/a 



According to an internal workaround master list, we need to set bit 5
of register 9400 to avoid issues with color blits.

Testing shows that this seems to fix the blitter hangs when fbc is
enabled on snb, thanks to Chris Wilson for figuring this out.

Tested-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Tested-by: default avatarMichael "brot" Groh <michael.groh@minad.de>
Acked-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-Off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 27c1cbd0

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -3728,6 +3728,9 @@ 
#define  GT_FIFO_FREE_ENTRIES			0x120008

#define    GT_FIFO_NUM_RESERVED_ENTRIES		20



#define GEN6_UCGCTL1				0x9400

# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE		(1 << 5)



#define GEN6_UCGCTL2				0x9404

# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)

# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1 << 12)

drivers/gpu/drm/i915/intel_display.c

+4 −0
Original line number Diff line number Diff line
@@ -8556,6 +8556,10 @@ static void gen6_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(WM2_LP_ILK, 0);

	I915_WRITE(WM1_LP_ILK, 0);



	I915_WRITE(GEN6_UCGCTL1,

		   I915_READ(GEN6_UCGCTL1) |

		   GEN6_BLBUNIT_CLOCK_GATE_DISABLE);



	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock

	 * gating disable must be set.  Failure to set it results in

	 * flickering pixels due to Z write ordering failures after