clk: msm: clock-cpu-8996: Remove primary PLL workaround on MSM8996V3



Test-control register programming across frequency changes
are no longer necessary on V3. Remove the workaround.

Change-Id: I2ce539c1e227cc143614a8b52348c8f22045fa0b
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>

parent 1472dfc5

drivers/clk/msm/clock-cpu-8996.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -1281,6 +1281,8 @@ int __init cpu_clock_8996_early_init(void)
		if (cpu_clocks_v3) {
		pwrcl_alt_pll.offline_bit_workaround = false;
		perfcl_alt_pll.offline_bit_workaround = false;
		pwrcl_pll.pgm_test_ctl_enable = false;
		perfcl_pll.pgm_test_ctl_enable = false;
		pwrcl_pll.vals.config_ctl_val = 0x200d4828;
		pwrcl_pll.vals.config_ctl_hi_val = 0x006;
		perfcl_pll.vals.config_ctl_val = 0x200d4828;