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Commit 80cb9a0f authored by Ben Hutchings's avatar Ben Hutchings Committed by David S. Miller
Browse files

sfc: Treat all MAC registers as 128-bit 



Although all the defined fields in these registers are within 32 bits,
they are architecturally defined as 128-bit like most other Falcon
registers.  In particular, we must use efx_reado() to ensure proper
locking when reading MD_STAT_REG.

Signed-off-by: default avatarBen Hutchings <bhutchings@solarflare.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 46e1ac0f

drivers/net/sfc/falcon.c

+7 −7
Original line number Original line Diff line number Diff line
@@ -2042,18 +2042,18 @@ int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset) 
/* Wait for GMII access to complete */

/* Wait for GMII access to complete */

static int falcon_gmii_wait(struct efx_nic *efx)

static int falcon_gmii_wait(struct efx_nic *efx)

{

{

	efx_dword_t md_stat;

	efx_oword_t md_stat;

	int count;

	int count;





	/* wait upto 50ms - taken max from datasheet */

	/* wait upto 50ms - taken max from datasheet */

	for (count = 0; count < 5000; count++) {

	for (count = 0; count < 5000; count++) {

		efx_readd(efx, &md_stat, FR_AB_MD_STAT);

		efx_reado(efx, &md_stat, FR_AB_MD_STAT);

		if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {

		if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {

			if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||

			if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||

			    EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {

			    EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {

				EFX_ERR(efx, "error from GMII access "

				EFX_ERR(efx, "error from GMII access "

					EFX_DWORD_FMT"\n",

					EFX_OWORD_FMT"\n",

					EFX_DWORD_VAL(md_stat));

					EFX_OWORD_VAL(md_stat));

				return -EIO;

				return -EIO;

			}

			}

			return 0;

			return 0;

drivers/net/sfc/falcon_xmac.c

+7 −7
Original line number Original line Diff line number Diff line
@@ -64,7 +64,7 @@ int falcon_reset_xaui(struct efx_nic *efx) 
	int count;

	int count;





	/* Start reset sequence */

	/* Start reset sequence */

	EFX_POPULATE_DWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1);

	EFX_POPULATE_OWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1);

	efx_writeo(efx, &reg, FR_AB_XX_PWR_RST);

	efx_writeo(efx, &reg, FR_AB_XX_PWR_RST);





	/* Wait up to 10 ms for completion, then reinitialise */

	/* Wait up to 10 ms for completion, then reinitialise */
@@ -146,14 +146,14 @@ static void falcon_reconfigure_xmac_core(struct efx_nic *efx) 
	bool rx_fc = !!(efx->link_state.fc & EFX_FC_RX);

	bool rx_fc = !!(efx->link_state.fc & EFX_FC_RX);





	/* Configure MAC  - cut-thru mode is hard wired on */

	/* Configure MAC  - cut-thru mode is hard wired on */

	EFX_POPULATE_DWORD_3(reg,

	EFX_POPULATE_OWORD_3(reg,

			     FRF_AB_XM_RX_JUMBO_MODE, 1,

			     FRF_AB_XM_RX_JUMBO_MODE, 1,

			     FRF_AB_XM_TX_STAT_EN, 1,

			     FRF_AB_XM_TX_STAT_EN, 1,

			     FRF_AB_XM_RX_STAT_EN, 1);

			     FRF_AB_XM_RX_STAT_EN, 1);

	efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);

	efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);





	/* Configure TX */

	/* Configure TX */

	EFX_POPULATE_DWORD_6(reg,

	EFX_POPULATE_OWORD_6(reg,

			     FRF_AB_XM_TXEN, 1,

			     FRF_AB_XM_TXEN, 1,

			     FRF_AB_XM_TX_PRMBL, 1,

			     FRF_AB_XM_TX_PRMBL, 1,

			     FRF_AB_XM_AUTO_PAD, 1,

			     FRF_AB_XM_AUTO_PAD, 1,
@@ -163,7 +163,7 @@ static void falcon_reconfigure_xmac_core(struct efx_nic *efx) 
	efx_writeo(efx, &reg, FR_AB_XM_TX_CFG);

	efx_writeo(efx, &reg, FR_AB_XM_TX_CFG);





	/* Configure RX */

	/* Configure RX */

	EFX_POPULATE_DWORD_5(reg,

	EFX_POPULATE_OWORD_5(reg,

			     FRF_AB_XM_RXEN, 1,

			     FRF_AB_XM_RXEN, 1,

			     FRF_AB_XM_AUTO_DEPAD, 0,

			     FRF_AB_XM_AUTO_DEPAD, 0,

			     FRF_AB_XM_ACPT_ALL_MCAST, 1,

			     FRF_AB_XM_ACPT_ALL_MCAST, 1,
@@ -173,14 +173,14 @@ static void falcon_reconfigure_xmac_core(struct efx_nic *efx) 




	/* Set frame length */

	/* Set frame length */

	max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);

	max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);

	EFX_POPULATE_DWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len);

	EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len);

	efx_writeo(efx, &reg, FR_AB_XM_RX_PARAM);

	efx_writeo(efx, &reg, FR_AB_XM_RX_PARAM);

	EFX_POPULATE_DWORD_2(reg,

	EFX_POPULATE_OWORD_2(reg,

			     FRF_AB_XM_MAX_TX_FRM_SIZE, max_frame_len,

			     FRF_AB_XM_MAX_TX_FRM_SIZE, max_frame_len,

			     FRF_AB_XM_TX_JUMBO_MODE, 1);

			     FRF_AB_XM_TX_JUMBO_MODE, 1);

	efx_writeo(efx, &reg, FR_AB_XM_TX_PARAM);

	efx_writeo(efx, &reg, FR_AB_XM_TX_PARAM);





	EFX_POPULATE_DWORD_2(reg,

	EFX_POPULATE_OWORD_2(reg,

			     FRF_AB_XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */

			     FRF_AB_XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */

			     FRF_AB_XM_DIS_FCNTL, !rx_fc);

			     FRF_AB_XM_DIS_FCNTL, !rx_fc);

	efx_writeo(efx, &reg, FR_AB_XM_FC);

	efx_writeo(efx, &reg, FR_AB_XM_FC);