Loading drivers/video/msm/mdss/mdss_dsi.h +2 −0 Original line number Diff line number Diff line Loading @@ -540,6 +540,8 @@ struct mdss_dsi_ctrl_pdata { bool timing_db_mode; bool update_phy_timing; /* flag to recalculate PHY timings */ bool phy_power_off; }; struct dsi_status_data { Loading drivers/video/msm/mdss/msm_mdss_io_8974.c +121 −11 Original line number Diff line number Diff line Loading @@ -53,6 +53,9 @@ #define DSIPHY_PLL_CLKBUFLR_EN 0x041c #define DSIPHY_PLL_PLL_BANDGAP 0x0508 #define DSIPHY_LANE_STRENGTH_CTRL_1 0x003c #define DSIPHY_LANE_VREG_CNTRL 0x0064 #define DSI_DYNAMIC_REFRESH_PLL_CTRL0 0x214 #define DSI_DYNAMIC_REFRESH_PLL_CTRL1 0x218 #define DSI_DYNAMIC_REFRESH_PLL_CTRL2 0x21C Loading Loading @@ -875,6 +878,92 @@ static void mdss_dsi_8996_phy_regulator_enable( } static void mdss_dsi_8996_phy_power_off( struct mdss_dsi_ctrl_pdata *ctrl) { int ln; void __iomem *base; MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, 0x7f); /* 4 lanes + clk lane configuration */ for (ln = 0; ln < 5; ln++) { base = ctrl->phy_io.base + DATALANE_OFFSET_FROM_BASE_8996; base += (ln * DATALANE_SIZE_8996); /* lane base */ /* turn off phy ldo */ MIPI_OUTP(base + DSIPHY_LANE_VREG_CNTRL, 0x1c); } MIPI_OUTP((ctrl->phy_io.base) + DSIPHY_CMN_LDO_CNTRL, 0x1c); /* 4 lanes + clk lane configuration */ for (ln = 0; ln < 5; ln++) { base = ctrl->phy_io.base + DATALANE_OFFSET_FROM_BASE_8996; base += (ln * DATALANE_SIZE_8996); /* lane base */ MIPI_OUTP(base + DSIPHY_LANE_STRENGTH_CTRL_1, 0x0); } wmb(); /* make sure registers committed */ } static void mdss_dsi_phy_power_off( struct mdss_dsi_ctrl_pdata *ctrl) { if (ctrl->phy_power_off) return; /* supported for phy rev 2.0 */ if (ctrl->shared_data->phy_rev != DSI_PHY_REV_20) return; mdss_dsi_8996_phy_power_off(ctrl); ctrl->phy_power_off = true; } static void mdss_dsi_8996_phy_power_on( struct mdss_dsi_ctrl_pdata *ctrl) { int j, off, ln, cnt, ln_off; void __iomem *base; struct mdss_dsi_phy_ctrl *pd; char *ip; pd = &(((ctrl->panel_data).panel_info.mipi).dsi_phy_db); /* 4 lanes + clk lane configuration */ for (ln = 0; ln < 5; ln++) { base = ctrl->phy_io.base + DATALANE_OFFSET_FROM_BASE_8996; base += (ln * DATALANE_SIZE_8996); /* lane base */ /* strength, 2 * 5 */ cnt = 2; ln_off = cnt * ln; ip = &pd->strength[ln_off]; off = 0x38; for (j = 0; j < cnt; j++, off += 4) MIPI_OUTP(base + off, *ip++); } mdss_dsi_8996_phy_regulator_enable(ctrl); } static void mdss_dsi_phy_power_on( struct mdss_dsi_ctrl_pdata *ctrl, bool mmss_clamp) { if (mmss_clamp && (ctrl->shared_data->phy_rev != DSI_PHY_REV_20)) mdss_dsi_phy_init(ctrl); else if ((ctrl->shared_data->phy_rev == DSI_PHY_REV_20) && ctrl->phy_power_off) mdss_dsi_8996_phy_power_on(ctrl); ctrl->phy_power_off = false; } static void mdss_dsi_8996_phy_config(struct mdss_dsi_ctrl_pdata *ctrl) { struct mdss_dsi_phy_ctrl *pd; Loading Loading @@ -1990,6 +2079,7 @@ int mdss_dsi_pre_clkoff_cb(void *priv, */ if ((ctrl->ctrl_state & CTRL_STATE_DSI_ACTIVE) || pdata->panel_info.ulps_suspend_enabled) { mdss_dsi_phy_power_off(ctrl); rc = mdss_dsi_clamp_ctrl(ctrl, 1); if (rc) pr_err("%s: Failed to enable dsi clamps. rc=%d\n", Loading @@ -2016,18 +2106,18 @@ int mdss_dsi_post_clkon_cb(void *priv, int rc = 0; struct mdss_panel_data *pdata = NULL; struct mdss_dsi_ctrl_pdata *ctrl = priv; bool mmss_clamp; pdata = &ctrl->panel_data; if (clk & MDSS_DSI_CORE_CLK) { mmss_clamp = ctrl->mmss_clamp; /* * Phy and controller setup is needed if coming out of idle * controller setup is needed if coming out of idle * power collapse with clamps enabled. */ if (ctrl->mmss_clamp) { mdss_dsi_phy_init(ctrl); if (mmss_clamp) mdss_dsi_ctrl_setup(ctrl); } if (ctrl->ulps) { /* Loading Loading @@ -2059,6 +2149,13 @@ int mdss_dsi_post_clkon_cb(void *priv, __func__, rc); goto error; } /* * Phy setup is needed if coming out of idle * power collapse with clamps enabled. */ if (ctrl->phy_power_off || mmss_clamp) mdss_dsi_phy_power_on(ctrl, mmss_clamp); } if (clk & MDSS_DSI_LINK_CLK) { if (ctrl->ulps) { Loading Loading @@ -2095,8 +2192,18 @@ int mdss_dsi_post_clkoff_cb(void *priv, pdata = &ctrl->panel_data; for (i = DSI_MAX_PM - 1; i >= DSI_CORE_PM; i--) { if ((i != DSI_CORE_PM) && (ctrl->ctrl_state & CTRL_STATE_DSI_ACTIVE)) /* * if DSI state is active * 1. allow to turn off the core power module. * 2. allow to turn off phy power module if it is * turned off * * allow to turn off all power modules if DSI is not * active */ if ((ctrl->ctrl_state & CTRL_STATE_DSI_ACTIVE) && (i != DSI_CORE_PM) && (ctrl->phy_power_off && (i != DSI_PHY_PM))) continue; rc = msm_dss_enable_vreg( sdata->power_data[i].vreg_config, Loading Loading @@ -2138,15 +2245,18 @@ int mdss_dsi_pre_clkon_cb(void *priv, * 1.> PANEL_PM are controlled as part of * panel_power_ctrl. Needed not be handled here. * 2.> CORE_PM are controlled by dsi clk manager. * 2.> PHY_PM and CTRL_PM need to be enabled/disabled * 3.> CTRL_PM need to be enabled/disabled * only during unblank/blank. Their state should * not be changed during static screen. * 4.> PHY_PM can be turned enabled/disabled * if phy regulators are enabled/disabled. */ pr_debug("%s: Enable DSI core power\n", __func__); for (i = DSI_CORE_PM; i < DSI_MAX_PM; i++) { if ((i != DSI_CORE_PM) && (ctrl->ctrl_state & CTRL_STATE_DSI_ACTIVE) && !pdata->panel_info.cont_splash_enabled) if ((ctrl->ctrl_state & CTRL_STATE_DSI_ACTIVE) && (!pdata->panel_info.cont_splash_enabled) && (i != DSI_CORE_PM) && (ctrl->phy_power_off && (i != DSI_PHY_PM))) continue; rc = msm_dss_enable_vreg( sdata->power_data[i].vreg_config, Loading Loading
drivers/video/msm/mdss/mdss_dsi.h +2 −0 Original line number Diff line number Diff line Loading @@ -540,6 +540,8 @@ struct mdss_dsi_ctrl_pdata { bool timing_db_mode; bool update_phy_timing; /* flag to recalculate PHY timings */ bool phy_power_off; }; struct dsi_status_data { Loading
drivers/video/msm/mdss/msm_mdss_io_8974.c +121 −11 Original line number Diff line number Diff line Loading @@ -53,6 +53,9 @@ #define DSIPHY_PLL_CLKBUFLR_EN 0x041c #define DSIPHY_PLL_PLL_BANDGAP 0x0508 #define DSIPHY_LANE_STRENGTH_CTRL_1 0x003c #define DSIPHY_LANE_VREG_CNTRL 0x0064 #define DSI_DYNAMIC_REFRESH_PLL_CTRL0 0x214 #define DSI_DYNAMIC_REFRESH_PLL_CTRL1 0x218 #define DSI_DYNAMIC_REFRESH_PLL_CTRL2 0x21C Loading Loading @@ -875,6 +878,92 @@ static void mdss_dsi_8996_phy_regulator_enable( } static void mdss_dsi_8996_phy_power_off( struct mdss_dsi_ctrl_pdata *ctrl) { int ln; void __iomem *base; MIPI_OUTP(ctrl->phy_io.base + DSIPHY_CMN_CTRL_0, 0x7f); /* 4 lanes + clk lane configuration */ for (ln = 0; ln < 5; ln++) { base = ctrl->phy_io.base + DATALANE_OFFSET_FROM_BASE_8996; base += (ln * DATALANE_SIZE_8996); /* lane base */ /* turn off phy ldo */ MIPI_OUTP(base + DSIPHY_LANE_VREG_CNTRL, 0x1c); } MIPI_OUTP((ctrl->phy_io.base) + DSIPHY_CMN_LDO_CNTRL, 0x1c); /* 4 lanes + clk lane configuration */ for (ln = 0; ln < 5; ln++) { base = ctrl->phy_io.base + DATALANE_OFFSET_FROM_BASE_8996; base += (ln * DATALANE_SIZE_8996); /* lane base */ MIPI_OUTP(base + DSIPHY_LANE_STRENGTH_CTRL_1, 0x0); } wmb(); /* make sure registers committed */ } static void mdss_dsi_phy_power_off( struct mdss_dsi_ctrl_pdata *ctrl) { if (ctrl->phy_power_off) return; /* supported for phy rev 2.0 */ if (ctrl->shared_data->phy_rev != DSI_PHY_REV_20) return; mdss_dsi_8996_phy_power_off(ctrl); ctrl->phy_power_off = true; } static void mdss_dsi_8996_phy_power_on( struct mdss_dsi_ctrl_pdata *ctrl) { int j, off, ln, cnt, ln_off; void __iomem *base; struct mdss_dsi_phy_ctrl *pd; char *ip; pd = &(((ctrl->panel_data).panel_info.mipi).dsi_phy_db); /* 4 lanes + clk lane configuration */ for (ln = 0; ln < 5; ln++) { base = ctrl->phy_io.base + DATALANE_OFFSET_FROM_BASE_8996; base += (ln * DATALANE_SIZE_8996); /* lane base */ /* strength, 2 * 5 */ cnt = 2; ln_off = cnt * ln; ip = &pd->strength[ln_off]; off = 0x38; for (j = 0; j < cnt; j++, off += 4) MIPI_OUTP(base + off, *ip++); } mdss_dsi_8996_phy_regulator_enable(ctrl); } static void mdss_dsi_phy_power_on( struct mdss_dsi_ctrl_pdata *ctrl, bool mmss_clamp) { if (mmss_clamp && (ctrl->shared_data->phy_rev != DSI_PHY_REV_20)) mdss_dsi_phy_init(ctrl); else if ((ctrl->shared_data->phy_rev == DSI_PHY_REV_20) && ctrl->phy_power_off) mdss_dsi_8996_phy_power_on(ctrl); ctrl->phy_power_off = false; } static void mdss_dsi_8996_phy_config(struct mdss_dsi_ctrl_pdata *ctrl) { struct mdss_dsi_phy_ctrl *pd; Loading Loading @@ -1990,6 +2079,7 @@ int mdss_dsi_pre_clkoff_cb(void *priv, */ if ((ctrl->ctrl_state & CTRL_STATE_DSI_ACTIVE) || pdata->panel_info.ulps_suspend_enabled) { mdss_dsi_phy_power_off(ctrl); rc = mdss_dsi_clamp_ctrl(ctrl, 1); if (rc) pr_err("%s: Failed to enable dsi clamps. rc=%d\n", Loading @@ -2016,18 +2106,18 @@ int mdss_dsi_post_clkon_cb(void *priv, int rc = 0; struct mdss_panel_data *pdata = NULL; struct mdss_dsi_ctrl_pdata *ctrl = priv; bool mmss_clamp; pdata = &ctrl->panel_data; if (clk & MDSS_DSI_CORE_CLK) { mmss_clamp = ctrl->mmss_clamp; /* * Phy and controller setup is needed if coming out of idle * controller setup is needed if coming out of idle * power collapse with clamps enabled. */ if (ctrl->mmss_clamp) { mdss_dsi_phy_init(ctrl); if (mmss_clamp) mdss_dsi_ctrl_setup(ctrl); } if (ctrl->ulps) { /* Loading Loading @@ -2059,6 +2149,13 @@ int mdss_dsi_post_clkon_cb(void *priv, __func__, rc); goto error; } /* * Phy setup is needed if coming out of idle * power collapse with clamps enabled. */ if (ctrl->phy_power_off || mmss_clamp) mdss_dsi_phy_power_on(ctrl, mmss_clamp); } if (clk & MDSS_DSI_LINK_CLK) { if (ctrl->ulps) { Loading Loading @@ -2095,8 +2192,18 @@ int mdss_dsi_post_clkoff_cb(void *priv, pdata = &ctrl->panel_data; for (i = DSI_MAX_PM - 1; i >= DSI_CORE_PM; i--) { if ((i != DSI_CORE_PM) && (ctrl->ctrl_state & CTRL_STATE_DSI_ACTIVE)) /* * if DSI state is active * 1. allow to turn off the core power module. * 2. allow to turn off phy power module if it is * turned off * * allow to turn off all power modules if DSI is not * active */ if ((ctrl->ctrl_state & CTRL_STATE_DSI_ACTIVE) && (i != DSI_CORE_PM) && (ctrl->phy_power_off && (i != DSI_PHY_PM))) continue; rc = msm_dss_enable_vreg( sdata->power_data[i].vreg_config, Loading Loading @@ -2138,15 +2245,18 @@ int mdss_dsi_pre_clkon_cb(void *priv, * 1.> PANEL_PM are controlled as part of * panel_power_ctrl. Needed not be handled here. * 2.> CORE_PM are controlled by dsi clk manager. * 2.> PHY_PM and CTRL_PM need to be enabled/disabled * 3.> CTRL_PM need to be enabled/disabled * only during unblank/blank. Their state should * not be changed during static screen. * 4.> PHY_PM can be turned enabled/disabled * if phy regulators are enabled/disabled. */ pr_debug("%s: Enable DSI core power\n", __func__); for (i = DSI_CORE_PM; i < DSI_MAX_PM; i++) { if ((i != DSI_CORE_PM) && (ctrl->ctrl_state & CTRL_STATE_DSI_ACTIVE) && !pdata->panel_info.cont_splash_enabled) if ((ctrl->ctrl_state & CTRL_STATE_DSI_ACTIVE) && (!pdata->panel_info.cont_splash_enabled) && (i != DSI_CORE_PM) && (ctrl->phy_power_off && (i != DSI_PHY_PM))) continue; rc = msm_dss_enable_vreg( sdata->power_data[i].vreg_config, Loading