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Commit 7f618945 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "defconfig: msm: Enable gic panic handler"

parents 81a98d6e 38a36d60
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+1 −0
Original line number Diff line number Diff line
@@ -542,6 +542,7 @@ CONFIG_SPDM_SCM=y
CONFIG_DEVFREQ_SPDM=y
CONFIG_PWM=y
CONFIG_PWM_QPNP=y
CONFIG_ARM_GIC_PANIC_HANDLER=y
CONFIG_CORESIGHT=y
CONFIG_CORESIGHT_EVENT=y
CONFIG_CORESIGHT_FUSE=y
+1 −0
Original line number Diff line number Diff line
@@ -487,6 +487,7 @@ CONFIG_MSM_IOMMU_V1=y
CONFIG_ARM_SMMU=y
CONFIG_PWM=y
CONFIG_PWM_QPNP=y
CONFIG_ARM_GIC_PANIC_HANDLER=y
CONFIG_CORESIGHT=y
CONFIG_CORESIGHT_EVENT=y
CONFIG_CORESIGHT_FUSE=y
+10 −0
Original line number Diff line number Diff line
@@ -16,6 +16,16 @@ config ARM_GIC_V3
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER

config ARM_GIC_PANIC_HANDLER
	bool "GIC Panic Handler"
	depends on ARM_GIC_V3 || ARM_GIC
	help
	  Save GIC distributor registers to RAM buffer on kernel panic.
	  gic-v3 will have an additional buffer for router registers.
	  Mainly for debugging purposes.

	  For production kernels, you should say 'N' here.

config ARM_NVIC
	bool
	select IRQ_DOMAIN
+31 −0
Original line number Diff line number Diff line
@@ -48,6 +48,10 @@ struct gic_chip_data {
	unsigned int wakeup_irqs[32];
	unsigned int enabled_irqs[32];
#endif
#ifdef CONFIG_ARM_GIC_PANIC_HANDLER
	u32 saved_dist_regs[0x400];
	u32 saved_router_regs[0x800];
#endif
};

static struct gic_chip_data gic_data __read_mostly;
@@ -302,6 +306,29 @@ static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
	return data->dist_base;
}

#ifdef CONFIG_ARM_GIC_PANIC_HANDLER
static int gic_panic_handler(struct notifier_block *this,
			unsigned long event, void *ptr)
{
	int i;
	void __iomem *base;

	base = gic_data.dist_base;
	for (i = 0; i < 0x400; i += 1)
		gic_data.saved_dist_regs[i] = readl_relaxed(base + 4 * i);

	base = gic_data.dist_base + GICD_IROUTER;
	for (i = 0; i < 0x800; i += 1)
		gic_data.saved_router_regs[i] = readl_relaxed(base + 4 * i);

	return NOTIFY_DONE;
}

static struct notifier_block gic_panic_blk = {
	.notifier_call = gic_panic_handler,
};
#endif

#ifdef CONFIG_PM
static int gic_suspend_one(struct gic_chip_data *gic)
{
@@ -864,6 +891,10 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
	gic_cpu_init();
	gic_cpu_pm_init();

#ifdef CONFIG_ARM_GIC_PANIC_HANDLER
	atomic_notifier_chain_register(&panic_notifier_list, &gic_panic_blk);
#endif

	return 0;

out_free:
+7 −0
Original line number Diff line number Diff line
@@ -76,7 +76,9 @@ struct gic_chip_data {
	unsigned int wakeup_irqs[32];
	unsigned int enabled_irqs[32];
#endif
#ifdef CONFIG_ARM_GIC_PANIC_HANDLER
	u32 saved_regs[0x400];
#endif
};

static DEFINE_RAW_SPINLOCK(irq_controller_lock);
@@ -181,6 +183,7 @@ static void gic_disable_irq(struct irq_data *d)
		gic_arch_extn.irq_disable(d);
}

#ifdef CONFIG_ARM_GIC_PANIC_HANDLER
static int gic_panic_handler(struct notifier_block *this,
			unsigned long event, void *ptr)
{
@@ -196,6 +199,7 @@ static int gic_panic_handler(struct notifier_block *this,
static struct notifier_block gic_panic_blk = {
	.notifier_call = gic_panic_handler,
};
#endif

#ifdef CONFIG_PM
static int gic_suspend_one(struct gic_chip_data *gic)
@@ -1219,7 +1223,10 @@ gic_of_init(struct device_node *node, struct device_node *parent)
		gic_cascade_irq(gic_cnt, irq);
	}
	gic_cnt++;

#ifdef CONFIG_ARM_GIC_PANIC_HANDLER
	atomic_notifier_chain_register(&panic_notifier_list, &gic_panic_blk);
#endif
	return 0;
}
IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);