Merge "Documentation: bindings: Modify Neutrino RMII option to u32" (7f01412b) · Commits · e / devices / android_kernel_xiaomi_markw

Documentation/devicetree/bindings/net/neutrino_avb.txt

+6 −1

Original line number	Diff line number	Diff line
		@@ -29,6 +29,10 @@ Optional properties:
		or approx 16.8 ms. For example, a value of 4 would
		mean a timestamp valid window of approximately 67
		ms.
		- qcom,ntn-rmii-mode: Use to select if RMII mode is enabled. The interface
		selection pin is not brought out so it has to be
		forced. If this option is omitted then RGMII mode
		will be used. Use 0 to disable and 1 to enable.

		Example:
		qcom,ntn_avb {
		@@ -44,7 +48,7 @@ Example:
		qcom,ntn-bus-num = <1>;
		};

		qcom,ntn_avb {
		ethernet {
		compatible = "qcom,ntn_avb";
		ntn-supply-enable-gpio = <&pmd9635_gpios 3 0>;
		qcom,ntn-rst-delay-msec = <100>;
		@@ -52,4 +56,5 @@ Example:
		qcom,ntn-fw-load-delay-msec = <200>;
		qcom,ntn-pcierst-resx;
		qcom,ntn-timestamp-valid-window = <4>; /* 4 is approx 67 ms */
		qcom,ntn-rmii-mode = <0>; /* RMII mode is disabled, use RGMII */
		};

arch/arm/boot/dts/qcom/Makefile

+2 −1

Original line number	Diff line number	Diff line
		@@ -162,7 +162,8 @@ dtb-$(CONFIG_ARCH_MDM9650) += mdm9650-sim.dtb \
		mdm9650-v1.1-emmc-mtp.dtb \
		mdm9650-v1.1-nand-mtp.dtb \
		mdm9650-v1.1-nand-dualwifi-mtp.dtb \
		mdm9650-v1.1-nand-ccard.dtb
		mdm9650-v1.1-nand-ccard.dtb \
		mdm9650-v1.1-nand-ccard-v2.dtb

		dtb-$(CONFIG_ARCH_SDX20) += sdx20-emmc-cdp.dtb \
		sdx20-emmc-mtp.dtb \

arch/arm/boot/dts/qcom/mdm9650-ccard.dtsi

+92 −23

Original line number	Diff line number	Diff line
		@@ -61,7 +61,7 @@
		asoc-codec-names = "tlv320aic3x-codec", "msm-stub-codec.1";
		};

		qcom,ntn_avb {
		ethernet {
		compatible = "qcom,ntn_avb";
		qcom,ntn-rst-delay-msec = <100>;
		qcom,ntn-rc-num = <0>;
		@@ -82,18 +82,6 @@
		/delete-property/ qca,bt-vdd-xtal-supply;
		};

		/* 1.1V/1.2V/1.8V/3.3V regulator for ethernet */
		ntn_vreg: regulator-ntn-tps65051 {
		compatible = "regulator-fixed";
		regulator-name = "ntn_vreg";
		startup-delay-us = <170>;
		gpio = <&tlmm_pinmux 69 0>;
		pinctrl-names = "default";
		pinctrl-0 = <&ntn_supply_gpio>;
		enable-active-high;
		regulator-always-on;
		};

		/* 4V regulator for peripherals */
		periph_vreg: regulator-periph-lm53635 {
		status = "disabled";
		@@ -162,7 +150,8 @@
		/* Set these up as hogs */
		pinctrl-names = "default";
		pinctrl-0 = <&can_reset_gpio>, <&ant_switch_gpio1>, <&ant_switch_gpio2>,
		<&ant_switch_gpio3>;
		<&ant_switch_gpio3>, <&eth_can_supply_gpio>,
		<&oabr_enable_gpio>;

		periph_vreg_gpio: periph_vreg_gpio {
		mux {
		@@ -176,8 +165,8 @@
		};
		};


		ntn_supply_gpio: ntn_supply_gpio {
		/* This gpio controls ETH supply on v1 and CAN supply on v2 */
		eth_can_supply_gpio: eth_can_supply_gpio {
		mux {
		pins = "gpio69";
		function = "gpio";
		@@ -186,7 +175,8 @@
		config {
		pins = "gpio69";
		drive-strength = <2>;
		bias-disable;
		output-high;
		bias-pull-up;
		};
		};

		@@ -204,6 +194,20 @@
		};
		};

		oabr_enable_gpio: oabr_enable_gpio {
		mux {
		pins = "gpio29";
		function = "gpio";
		};

		config {
		pins = "gpio29";
		drive-strength = <2>;
		output-high;
		bias-pull-up;
		};
		};

		pmx_sec_mi2s_dout {
		sec_mi2s_ws_sleep {
		mux {
		@@ -364,6 +368,58 @@
		};
		};
		};

		bmi160_int1_default: bmi160_int1_default {
		mux {
		pins = "gpio81";
		function = "gpio";
		};
		config {
		pins = "gpio81";
		drive-strength = <16>; /* 16 mA */
		bias-pull-down; /* pull down */
		};
		};

		bmi160_int2_default: bmi160_int2_default {
		mux {
		pins = "gpio94";
		function = "gpio";
		};
		config {
		pins = "gpio94";
		drive-strength = <16>; /* 16 mA */
		bias-pull-down; /* pull down */
		};
		};

		i2c_1b {
		i2c_1b_active: i2c_1b_active {
		mux {
		pins = "gpio84", "gpio85";
		function = "blsp_i2c1";
		};

		config {
		pins = "gpio84", "gpio85";
		drive-strength = <2>;
		bias-disable;
		};
		};

		i2c_1b_sleep: i2c_1b_sleep {
		mux {
		pins = "gpio84", "gpio85";
		function = "blsp_i2c1";
		};

		config {
		pins = "gpio84", "gpio85";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};
		};

		&cnss_pcie {
		@@ -391,6 +447,12 @@
		status = "ok";
		};

		&i2c_1 {
		status = "ok";
		pinctrl-0 = <&i2c_1b_active>;
		pinctrl-1 = <&i2c_1b_sleep>;
		};

		&i2c_3 {
		status = "ok";

		@@ -415,6 +477,18 @@
		compatible = "st,lsm330-accel";
		reg = <0x1d>;
		};

		bmi160@68 {
		compatible = "bosch-sensortec,bmi160";
		reg = <0x68>;
		pinctrl-names = "default";
		pinctrl-0 = <&bmi160_int1_default &bmi160_int2_default>;
		interrupt-parent = <&tlmm_pinmux>;
		interrupts = <81 0x2002>;
		bmi,init-interval = <200>;
		bmi,place = <1>;
		bmi,gpio_irq = <&tlmm_pinmux 81 0x2002>;
		};
		};

		&spi_4 {
		@@ -423,11 +497,6 @@
		};

		&usb3 {
		/* Disable pmic_id_irq due to HW glitch */
		interrupt-map = <0x0 0 &intc 0 202 0
		0x0 1 &intc 0 203 0
		0x0 2 &intc 0 180 0>;
		interrupt-names = "hs_phy_irq", "ss_phy_irq", "pwr_event_irq";
		qcom,charging-disabled;
		};

		@@ -456,7 +525,7 @@
		qcom,master-en = <0>; /* DISABLE GPIO */
		};

		gpio@c200 { /* GPIO 3 - CAN_EN */
		gpio@c200 { /* GPIO 3 - CAN_ETH_EN, CAN on v1 and ETH on v2 */
		status = "ok";
		qcom,mode = <1>; /* Digital output*/
		qcom,output-type = <0>; /* CMOS logic */

arch/arm/boot/dts/qcom/mdm9650-v1.1-nand-ccard-v2.dts

0 → 100644

+42 −0

Original line number	Diff line number	Diff line
		/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		* only version 2 as published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		/dts-v1/;

		#include "mdm9650-ccard.dtsi"

		/ {
		model = "Qualcomm Technologies, Inc. MDM 9650 v1.1 CCARD (NAND) v2";
		compatible = "qcom,mdm9650-mtp", "qcom,mdm9650",
		"qcom,mtp";
		qcom,board-id = <0x20008 0x6>, <0x20008 0x106>;
		};

		&qnand_1 {
		status = "ok";
		};

		&soc {
		ethernet {
		ntn-supply-enable-gpio = <&pmd9650_gpios 3 0>;
		};
		};

		&usb3 {
		/* Enable USB detection on v2 */
		interrupt-map = <0x0 0 &intc 0 202 0
		0x0 1 &intc 0 203 0
		0x0 2 &intc 0 180 0
		0x0 3 &spmi_bus 0x0 0x0 0xc4 0x0>;
		interrupt-names = "hs_phy_irq", "ss_phy_irq", "pwr_event_irq",
		"pmic_id_irq";
		};

arch/arm/boot/dts/qcom/mdm9650-v1.1-nand-ccard.dts

+9 −1

Original line number	Diff line number	Diff line
		@@ -18,9 +18,17 @@
		model = "Qualcomm Technologies, Inc. MDM 9650 v1.1 CCARD (NAND)";
		compatible = "qcom,mdm9650-mtp", "qcom,mdm9650",
		"qcom,mtp";
		qcom,board-id = <8 0x6>, <8 0x106>;
		qcom,board-id = <0x10008 0x6>, <0x10008 0x106>;
		};

		&qnand_1 {
		status = "ok";
		};

		&usb3 {
		/* Disable pmic_id_irq due to HW glitch */
		interrupt-map = <0x0 0 &intc 0 202 0
		0x0 1 &intc 0 203 0
		0x0 2 &intc 0 180 0>;
		interrupt-names = "hs_phy_irq", "ss_phy_irq", "pwr_event_irq";
		};