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Commit 7ebc90a2 authored by Tirupathi Reddy's avatar Tirupathi Reddy
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ARM: dts: msm: Configure Temp based adjustments for msm8953



Temperature based voltage adjustments logic maintains the
optimum rail voltage based on the input temperature data
from tsens controller.

CRs-Fixed: 1027915
Change-Id: I51b459ff4d8416b39c2d002f0e2e974edd9a902f
Signed-off-by: default avatarTirupathi Reddy <tirupath@codeaurora.org>
parent cc957303
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+46 −0
Original line number Diff line number Diff line
@@ -378,6 +378,9 @@
			"APCS_ALIAS0_APM_CTLER_STATUS",
			"APCS0_CPR_CORE_ADJ_MODE_REG";

		qcom,cpr-temp-point-map = <250 650 850>;
		qcom,cpr-initial-temp-band = <0>;

		thread@0 {
			qcom,cpr-thread-id = <0>;
			qcom,cpr-consecutive-up = <0>;
@@ -734,6 +737,49 @@
				qcom,allow-voltage-interpolation;
				qcom,allow-quotient-interpolation;
				qcom,cpr-scaled-open-loop-voltage-as-ceiling;

				qcom,corner-allow-temp-adjustment =
					/* Speed bin 0; CPR rev 0..7 */
					<0 0 0 0 0 0 0 0 0>,
					<0 0 0 0 0 0 0 0 0>,
					<0 0 0 0 0 0 0 0 0>,
					<1 1 1 1 0 0 0 0 0>,
					<1 1 1 1 0 0 0 0 0>,
					<1 1 1 1 0 0 0 0 0>,
					<1 1 1 1 0 0 0 0 0>,
					<1 1 1 1 0 0 0 0 0>,

					/* Speed bin 2; CPR rev 0..7 */
					<0 0 0 0 0 0 0>,
					<0 0 0 0 0 0 0>,
					<0 0 0 0 0 0 0>,
					<1 1 1 1 0 0 0>,
					<1 1 1 1 0 0 0>,
					<1 1 1 1 0 0 0>,
					<1 1 1 1 0 0 0>,
					<1 1 1 1 0 0 0>,

					/* Speed bin 7; CPR rev 0..7 */
					<0 0 0 0 0 0 0 0 0>,
					<0 0 0 0 0 0 0 0 0>,
					<0 0 0 0 0 0 0 0 0>,
					<1 1 1 1 0 0 0 0 0>,
					<1 1 1 1 0 0 0 0 0>,
					<1 1 1 1 0 0 0 0 0>,
					<1 1 1 1 0 0 0 0 0>,
					<1 1 1 1 0 0 0 0 0>;

				qcom,cpr-corner1-temp-core-voltage-adjustment =
					<(0) (-5000) (-15000) (-20000)>;

				qcom,cpr-corner2-temp-core-voltage-adjustment =
					<(0) (-5000) (-15000) (-15000)>;

				qcom,cpr-corner3-temp-core-voltage-adjustment =
					<(0) (-5000) (-15000)      (0)>;

				qcom,cpr-corner4-temp-core-voltage-adjustment =
					<(0) (-5000) (-15000)      (0)>;
			};
		};
	};