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Commit 7ebad705 authored by Dave Jones's avatar Dave Jones Committed by Ingo Molnar
Browse files

x86: use CR0 defines. 



Signed-off-by: default avatarDave Jones <davej@redhat.com>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 3578facf

arch/x86/kernel/cpu/bugs.c

+2 −1
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
#include <linux/utsname.h>

#include <asm/bugs.h>

#include <asm/processor.h>

#include <asm/processor-flags.h>

#include <asm/i387.h>

#include <asm/msr.h>

#include <asm/paravirt.h>
@@ -35,7 +36,7 @@ __setup("mca-pentium", mca_pentium); 
static int __init no_387(char *s)

{

	boot_cpu_data.hard_math = 0;

	write_cr0(0xE | read_cr0());

	write_cr0(X86_CR0_TS | X86_CR0_EM | X86_CR0_MP | read_cr0());

	return 1;

}

arch/x86/kernel/cpu/cyrix.c

+2 −4
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ 
#include <asm/dma.h>

#include <asm/io.h>

#include <asm/processor-cyrix.h>

#include <asm/processor-flags.h>

#include <asm/timer.h>

#include <asm/pci-direct.h>

#include <asm/tsc.h>
@@ -126,15 +127,12 @@ static void __cpuinit set_cx86_reorder(void) 


static void __cpuinit set_cx86_memwb(void)

{

	u32 cr0;



	printk(KERN_INFO "Enable Memory-Write-back mode on Cyrix/NSC processor.\n");



	/* CCR2 bit 2: unlock NW bit */

	setCx86(CX86_CCR2, getCx86(CX86_CCR2) & ~0x04);

	/* set 'Not Write-through' */

	cr0 = 0x20000000;

	write_cr0(read_cr0() | cr0);

	write_cr0(read_cr0() | X86_CR0_NW);

	/* CCR2 bit 2: lock NW bit and set WT1 */

	setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14 );

}

arch/x86/kernel/cpu/mtrr/cyrix.c

+2 −1
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
#include <asm/msr.h>

#include <asm/io.h>

#include <asm/processor-cyrix.h>

#include <asm/processor-flags.h>

#include "mtrr.h"



int arr3_protected;
@@ -142,7 +143,7 @@ static void prepare_set(void) 


	/*  Disable and flush caches. Note that wbinvd flushes the TLBs as

	    a side-effect  */

	cr0 = read_cr0() | 0x40000000;

	cr0 = read_cr0() | X86_CR0_CD;

	wbinvd();

	write_cr0(cr0);

	wbinvd();

arch/x86/kernel/cpu/mtrr/generic.c

+2 −1
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
#include <asm/msr.h>

#include <asm/system.h>

#include <asm/cpufeature.h>

#include <asm/processor-flags.h>

#include <asm/tlbflush.h>

#include "mtrr.h"
@@ -350,7 +351,7 @@ static void prepare_set(void) __acquires(set_atomicity_lock) 
	spin_lock(&set_atomicity_lock);



	/*  Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */

	cr0 = read_cr0() | 0x40000000;	/* set CD flag */

	cr0 = read_cr0() | X86_CR0_CD;

	write_cr0(cr0);

	wbinvd();

arch/x86/kernel/cpu/mtrr/state.c

+2 −1
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
#include <asm/mtrr.h>

#include <asm/msr.h>

#include <asm/processor-cyrix.h>

#include <asm/processor-flags.h>

#include "mtrr.h"
@@ -25,7 +26,7 @@ void set_mtrr_prepare_save(struct set_mtrr_context *ctxt) 


		/*  Disable and flush caches. Note that wbinvd flushes the TLBs as

		    a side-effect  */

		cr0 = read_cr0() | 0x40000000;

		cr0 = read_cr0() | X86_CR0_CD;

		wbinvd();

		write_cr0(cr0);

		wbinvd();