Loading drivers/iommu/arm-smmu.c +4 −9 Original line number Diff line number Diff line Loading @@ -293,13 +293,6 @@ #define FSYNR0_WNR (1 << 4) #define ARM_SMMU_IMPL_DEF0(smmu) \ ((smmu)->base + (2 * (1 << (smmu)->pgshift))) #define ARM_SMMU_IMPL_DEF1(smmu) \ ((smmu)->base + (6 * (1 << (smmu)->pgshift))) #define IMPL_DEF1_MICRO_MMU_CTRL 0 #define MICRO_MMU_CTRL_LOCAL_HALT_REQ (1 << 2) static int force_stage; module_param_named(force_stage, force_stage, int, S_IRUGO | S_IWUSR); MODULE_PARM_DESC(force_stage, Loading Loading @@ -2243,10 +2236,12 @@ static int arm_smmu_wait_for_halt(struct arm_smmu_device *smmu) static int __arm_smmu_halt(struct arm_smmu_device *smmu, bool wait) { u32 reg; void __iomem *impl_def1_base = ARM_SMMU_IMPL_DEF1(smmu); writel_relaxed(MICRO_MMU_CTRL_LOCAL_HALT_REQ, impl_def1_base + IMPL_DEF1_MICRO_MMU_CTRL); reg = readl_relaxed(impl_def1_base + IMPL_DEF1_MICRO_MMU_CTRL); reg |= MICRO_MMU_CTRL_LOCAL_HALT_REQ; writel_relaxed(reg, impl_def1_base + IMPL_DEF1_MICRO_MMU_CTRL); return wait ? arm_smmu_wait_for_halt(smmu) : 0; } Loading Loading
drivers/iommu/arm-smmu.c +4 −9 Original line number Diff line number Diff line Loading @@ -293,13 +293,6 @@ #define FSYNR0_WNR (1 << 4) #define ARM_SMMU_IMPL_DEF0(smmu) \ ((smmu)->base + (2 * (1 << (smmu)->pgshift))) #define ARM_SMMU_IMPL_DEF1(smmu) \ ((smmu)->base + (6 * (1 << (smmu)->pgshift))) #define IMPL_DEF1_MICRO_MMU_CTRL 0 #define MICRO_MMU_CTRL_LOCAL_HALT_REQ (1 << 2) static int force_stage; module_param_named(force_stage, force_stage, int, S_IRUGO | S_IWUSR); MODULE_PARM_DESC(force_stage, Loading Loading @@ -2243,10 +2236,12 @@ static int arm_smmu_wait_for_halt(struct arm_smmu_device *smmu) static int __arm_smmu_halt(struct arm_smmu_device *smmu, bool wait) { u32 reg; void __iomem *impl_def1_base = ARM_SMMU_IMPL_DEF1(smmu); writel_relaxed(MICRO_MMU_CTRL_LOCAL_HALT_REQ, impl_def1_base + IMPL_DEF1_MICRO_MMU_CTRL); reg = readl_relaxed(impl_def1_base + IMPL_DEF1_MICRO_MMU_CTRL); reg |= MICRO_MMU_CTRL_LOCAL_HALT_REQ; writel_relaxed(reg, impl_def1_base + IMPL_DEF1_MICRO_MMU_CTRL); return wait ? arm_smmu_wait_for_halt(smmu) : 0; } Loading