Merge "ARM: dts: msm: smmu: Add smmu device tree file for cobalt"

/* Copyright (c) 2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

#include <dt-bindings/clock/msm-clocks-cobalt.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

&soc {

	anoc1_smmu: arm,smmu-anoc1@1680000 {

		status = "ok";

		compatible = "qcom,smmu-v2";

		reg = <0x1680000 0x10000>;

		#iommu-cells = <1>;

		qcom,register-save;

		qcom,skip-init;

		#global-interrupts = <2>;

		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&clock_gcc clk_aggre1_noc_clk>;

		clock-names = "smmu_aggre1_noc_clk";

		#clock-cells = <1>;

	};

	anoc2_smmu: arm,smmu-anoc2@16c0000 {

		status = "ok";

		compatible = "qcom,smmu-v2";

		reg = <0x16c0000 0x40000>;

		#iommu-cells = <1>;

		qcom,register-save;

		qcom,skip-init;

		#global-interrupts = <2>;

		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&clock_gcc clk_aggre2_noc_clk>;

		clock-names = "smmu_aggre2_noc_clk";

		#clock-cells = <1>;

	};

	lpass_q6_smmu: arm,smmu-lpass_q6@5100000 {

		status = "ok";

		compatible = "qcom,smmu-v2";

		reg = <0x5100000 0x4000>;

		#iommu-cells = <1>;

		qcom,tz-device-id = "LPASS";

		qcom,register-save;

		qcom,skip-init;

		#global-interrupts = <2>;

		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;

		vdd-supply = <&gdsc_hlos1_vote_lpass_adsp>;

		clocks = <&clock_gcc clk_hlos1_vote_lpass_adsp_smmu_clk>;

		clock-names = "lpass_q6_smmu_clk";

		#clock-cells = <1>;

	};

	mmss_smmu: arm,smmu-mmss@cd00000 {

		status = "ok";

		compatible = "qcom,smmu-v2";

		reg = <0xcd00000 0x40000>;

		#iommu-cells = <1>;

		qcom,register-save;

		qcom,skip-init;

		#global-interrupts = <2>;

		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;

		vdd-supply = <&gdsc_bimc_smmu>;

		clocks = <&clock_mmss clk_bimc_smmu_ahb_clk>,

			<&clock_mmss clk_bimc_smmu_axi_clk>;

		clock-names = "mmss_smmu_ahb_clk", "mmss_smmu_axi_clk";

		#clock-cells = <1>;

	};

	kgsl_smmu: arm,smmu-kgsl@5040000 {

		status = "ok";

		compatible = "qcom,smmu-v2";

		reg = <0x5040000 0x10000>;

		#iommu-cells = <1>;

		qcom-tz-device-id = "GPU";

		qcom,dynamic;

		qcom,register-save;

		qcom,skip-init;

		#global-interrupts = <2>;

		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

			   <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;

		vdd-supply = <&gdsc_hlos1_vote_gpu_smmu>;

		clocks = <&clock_gcc clk_gcc_bimc_gfx_clk>;

		clock-name = "kgsl_smmu_clk";

		#clock-cells = <1>;

	};

};

&gdsc_gpu_cx {

	status = "ok";

};

#include "msm-arm-smmu-cobalt.dtsi"