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Commit 7e180bd8 authored by Martin Schwidefsky's avatar Martin Schwidefsky
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[S390] rename lowcore field



The 16 bit value at the lowcore location with offset 0x84 is the
cpu address that is associated with an external interrupt. Rename
the field from cpu_addr to ext_cpu_addr to make that clear.

Signed-off-by: default avatarMartin Schwidefsky <schwidefsky@de.ibm.com>
parent 4fdf7f43
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+2 −2
Original line number Diff line number Diff line
@@ -56,7 +56,7 @@ struct _lowcore {
	psw_t	mcck_new_psw;			/* 0x0070 */
	psw_t	io_new_psw;			/* 0x0078 */
	__u32	ext_params;			/* 0x0080 */
	__u16	cpu_addr;			/* 0x0084 */
	__u16	ext_cpu_addr;			/* 0x0084 */
	__u16	ext_int_code;			/* 0x0086 */
	__u16	svc_ilc;			/* 0x0088 */
	__u16	svc_code;			/* 0x008a */
@@ -189,7 +189,7 @@ struct _lowcore {
	__u32	ipl_parmblock_ptr;		/* 0x0014 */
	__u8	pad_0x0018[0x0080-0x0018];	/* 0x0018 */
	__u32	ext_params;			/* 0x0080 */
	__u16	cpu_addr;			/* 0x0084 */
	__u16	ext_cpu_addr;			/* 0x0084 */
	__u16	ext_int_code;			/* 0x0086 */
	__u16	svc_ilc;			/* 0x0088 */
	__u16	svc_code;			/* 0x008a */
+1 −1
Original line number Diff line number Diff line
@@ -78,7 +78,7 @@ int main(void)
	BLANK();
	/* lowcore offsets */
	DEFINE(__LC_EXT_PARAMS, offsetof(struct _lowcore, ext_params));
	DEFINE(__LC_CPU_ADDRESS, offsetof(struct _lowcore, cpu_addr));
	DEFINE(__LC_EXT_CPU_ADDR, offsetof(struct _lowcore, ext_cpu_addr));
	DEFINE(__LC_EXT_INT_CODE, offsetof(struct _lowcore, ext_int_code));
	DEFINE(__LC_SVC_ILC, offsetof(struct _lowcore, svc_ilc));
	DEFINE(__LC_SVC_INT_CODE, offsetof(struct _lowcore, svc_code));
+1 −1
Original line number Diff line number Diff line
@@ -606,7 +606,7 @@ ext_skip:
	stm	%r8,%r9,__PT_PSW(%r11)
	TRACE_IRQS_OFF
	lr	%r2,%r11		# pass pointer to pt_regs
	l	%r3,__LC_CPU_ADDRESS	# get cpu address + interruption code
	l	%r3,__LC_EXT_CPU_ADDR	# get cpu address + interruption code
	l	%r4,__LC_EXT_PARAMS	# get external parameters
	l	%r1,BASED(.Ldo_extint)
	basr	%r14,%r1		# call do_extint
+1 −1
Original line number Diff line number Diff line
@@ -625,7 +625,7 @@ ext_skip:
	TRACE_IRQS_OFF
	lghi	%r1,4096
	lgr	%r2,%r11		# pass pointer to pt_regs
	llgf	%r3,__LC_CPU_ADDRESS	# get cpu address + interruption code
	llgf	%r3,__LC_EXT_CPU_ADDR	# get cpu address + interruption code
	llgf	%r4,__LC_EXT_PARAMS	# get external parameter
	lg	%r5,__LC_EXT_PARAMS2-4096(%r1)	# get 64 bit external parameter
	brasl	%r14,do_extint
+2 −2
Original line number Diff line number Diff line
@@ -42,7 +42,7 @@ ENTRY(swsusp_arch_suspend)
	lghi	%r1,0x1000

	/* Save CPU address */
	stap	__LC_CPU_ADDRESS(%r0)
	stap	__LC_EXT_CPU_ADDR(%r0)

	/* Store registers */
	mvc	0x318(4,%r1),__SF_EMPTY(%r15)	/* move prefix to lowcore */
@@ -173,7 +173,7 @@ pgm_check_entry:
	larl	%r1,.Lresume_cpu		/* Resume CPU address: r2 */
	stap	0(%r1)
	llgh	%r2,0(%r1)
	llgh	%r1,__LC_CPU_ADDRESS(%r0)	/* Suspend CPU address: r1 */
	llgh	%r1,__LC_EXT_CPU_ADDR(%r0)	/* Suspend CPU address: r1 */
	cgr	%r1,%r2
	je	restore_registers		/* r1 = r2 -> nothing to do */
	larl	%r4,.Lrestart_suspend_psw	/* Set new restart PSW */
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