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Commit 7e03cc68 authored by Adrian Salido-Moreno's avatar Adrian Salido-Moreno Committed by Gerrit - the friendly Code Review server
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msm: mdss: add support for additional DMA pipes 



MDP revisions 3.0+ support more DMA pipes, provide support for using
and programming these pipes into layer mixer.

CRs-Fixed: 987777
Change-Id: Ice6d657fbe1410a2cfcb2afe089f894ef253410b
Signed-off-by: default avatarAdrian Salido-Moreno <adrianm@codeaurora.org>
parent 08939e92

drivers/video/msm/mdss/mdss_mdp.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -155,6 +155,8 @@ get_pipe_type_from_num(enum mdss_mdp_sspp_index pnum) 
		break;

		break;

	case MDSS_MDP_SSPP_DMA0:

	case MDSS_MDP_SSPP_DMA0:

	case MDSS_MDP_SSPP_DMA1:

	case MDSS_MDP_SSPP_DMA1:

	case MDSS_MDP_SSPP_DMA2:

	case MDSS_MDP_SSPP_DMA3:

		ptype = MDSS_MDP_PIPE_TYPE_DMA;

		ptype = MDSS_MDP_PIPE_TYPE_DMA;

		break;

		break;

	case MDSS_MDP_SSPP_CURSOR0:

	case MDSS_MDP_SSPP_CURSOR0:

drivers/video/msm/mdss/mdss_mdp_ctl.c

+6 −1
Original line number Original line Diff line number Diff line
@@ -27,7 +27,7 @@ 
#include "mdss_mdp_trace.h"

#include "mdss_mdp_trace.h"

#include "mdss_debug.h"

#include "mdss_debug.h"





#define NUM_MIXERCFG_REGS 2

#define NUM_MIXERCFG_REGS 3

#define MDSS_MDP_WB_OUTPUT_BPP	3

#define MDSS_MDP_WB_OUTPUT_BPP	3

struct mdss_mdp_mixer_cfg {

struct mdss_mdp_mixer_cfg {

	u32 config_masks[NUM_MIXERCFG_REGS];

	u32 config_masks[NUM_MIXERCFG_REGS];
@@ -39,6 +39,7 @@ static struct { 
	u32 flush_bit;

	u32 flush_bit;

	struct mdss_mdp_hwio_cfg base;

	struct mdss_mdp_hwio_cfg base;

	struct mdss_mdp_hwio_cfg ext;

	struct mdss_mdp_hwio_cfg ext;

	struct mdss_mdp_hwio_cfg ext2;

} mdp_pipe_hwio[MDSS_MDP_MAX_SSPP] = {

} mdp_pipe_hwio[MDSS_MDP_MAX_SSPP] = {

	[MDSS_MDP_SSPP_VIG0]    = {  0, {  0, 3, 0 }, {  0, 1, 3 } },

	[MDSS_MDP_SSPP_VIG0]    = {  0, {  0, 3, 0 }, {  0, 1, 3 } },

	[MDSS_MDP_SSPP_VIG1]    = {  1, {  3, 3, 0 }, {  2, 1, 3 } },

	[MDSS_MDP_SSPP_VIG1]    = {  1, {  3, 3, 0 }, {  2, 1, 3 } },
@@ -50,6 +51,8 @@ static struct { 
	[MDSS_MDP_SSPP_RGB3]    = { 19, { 29, 3, 0 }, { 14, 1, 3 } },

	[MDSS_MDP_SSPP_RGB3]    = { 19, { 29, 3, 0 }, { 14, 1, 3 } },

	[MDSS_MDP_SSPP_DMA0]    = { 11, { 18, 3, 0 }, { 16, 1, 3 } },

	[MDSS_MDP_SSPP_DMA0]    = { 11, { 18, 3, 0 }, { 16, 1, 3 } },

	[MDSS_MDP_SSPP_DMA1]    = { 12, { 21, 3, 0 }, { 18, 1, 3 } },

	[MDSS_MDP_SSPP_DMA1]    = { 12, { 21, 3, 0 }, { 18, 1, 3 } },

	[MDSS_MDP_SSPP_DMA2]    = { 24, .ext2 = {  0, 4, 0 } },

	[MDSS_MDP_SSPP_DMA3]    = { 25, .ext2 = {  4, 4, 0 } },

	[MDSS_MDP_SSPP_CURSOR0] = { 22, .ext  = { 20, 4, 0 } },

	[MDSS_MDP_SSPP_CURSOR0] = { 22, .ext  = { 20, 4, 0 } },

	[MDSS_MDP_SSPP_CURSOR1] = { 23, .ext  = { 26, 4, 0 } },

	[MDSS_MDP_SSPP_CURSOR1] = { 23, .ext  = { 26, 4, 0 } },

};

};
@@ -4043,6 +4046,7 @@ static void __mdss_mdp_mixer_update_cfg_masks(u32 pnum, u32 stage, 




	masks[0] = mdss_mdp_hwio_mask(&mdp_pipe_hwio[pnum].base, stage);

	masks[0] = mdss_mdp_hwio_mask(&mdp_pipe_hwio[pnum].base, stage);

	masks[1] = mdss_mdp_hwio_mask(&mdp_pipe_hwio[pnum].ext, stage);

	masks[1] = mdss_mdp_hwio_mask(&mdp_pipe_hwio[pnum].ext, stage);

	masks[2] = mdss_mdp_hwio_mask(&mdp_pipe_hwio[pnum].ext2, stage);





	for (i = 0; i < NUM_MIXERCFG_REGS; i++)

	for (i = 0; i < NUM_MIXERCFG_REGS; i++)

		cfg->config_masks[i] |= masks[i];

		cfg->config_masks[i] |= masks[i];
@@ -4058,6 +4062,7 @@ static void __mdss_mdp_mixer_get_offsets(u32 mixer_num, 




	offsets[0] = MDSS_MDP_REG_CTL_LAYER(mixer_num);

	offsets[0] = MDSS_MDP_REG_CTL_LAYER(mixer_num);

	offsets[1] = MDSS_MDP_REG_CTL_LAYER_EXTN(mixer_num);

	offsets[1] = MDSS_MDP_REG_CTL_LAYER_EXTN(mixer_num);

	offsets[2] = MDSS_MDP_REG_CTL_LAYER_EXTN2(mixer_num);

}

}





static inline int __mdss_mdp_mixer_get_hw_num(struct mdss_mdp_mixer *mixer)

static inline int __mdss_mdp_mixer_get_hw_num(struct mdss_mdp_mixer *mixer)

drivers/video/msm/mdss/mdss_mdp_hwio.h

+7 −1
Original line number Original line Diff line number Diff line
@@ -160,6 +160,7 @@ enum mdss_mdp_ctl_index { 








#define MDSS_MDP_REG_CTL_LAYER_EXTN_OFFSET		0x40

#define MDSS_MDP_REG_CTL_LAYER_EXTN_OFFSET		0x40

#define MDSS_MDP_REG_CTL_LAYER_EXTN2_OFFSET		0x70

#define MDSS_MDP_CTL_X_LAYER_5				0x24

#define MDSS_MDP_CTL_X_LAYER_5				0x24





/* mixer 5 has different offset than others */

/* mixer 5 has different offset than others */
@@ -169,6 +170,9 @@ enum mdss_mdp_ctl_index { 
#define MDSS_MDP_REG_CTL_LAYER_EXTN(lm)	\

#define MDSS_MDP_REG_CTL_LAYER_EXTN(lm)	\

	 (MDSS_MDP_REG_CTL_LAYER_EXTN_OFFSET + ((lm) * 0x004))

	 (MDSS_MDP_REG_CTL_LAYER_EXTN_OFFSET + ((lm) * 0x004))





#define MDSS_MDP_REG_CTL_LAYER_EXTN2(lm)	\

	 (MDSS_MDP_REG_CTL_LAYER_EXTN2_OFFSET + ((lm) * 0x004))



#define MDSS_MDP_REG_CTL_TOP				0x014

#define MDSS_MDP_REG_CTL_TOP				0x014

#define MDSS_MDP_REG_CTL_FLUSH				0x018

#define MDSS_MDP_REG_CTL_FLUSH				0x018

#define MDSS_MDP_REG_CTL_START				0x01C

#define MDSS_MDP_REG_CTL_START				0x01C
@@ -203,7 +207,9 @@ enum mdss_mdp_sspp_index { 
	MDSS_MDP_SSPP_RGB3,

	MDSS_MDP_SSPP_RGB3,

	MDSS_MDP_SSPP_CURSOR0,

	MDSS_MDP_SSPP_CURSOR0,

	MDSS_MDP_SSPP_CURSOR1,

	MDSS_MDP_SSPP_CURSOR1,

	MDSS_MDP_MAX_SSPP

	MDSS_MDP_SSPP_DMA2,

	MDSS_MDP_SSPP_DMA3,

	MDSS_MDP_MAX_SSPP,

};

};





enum mdss_mdp_sspp_fetch_type {

enum mdss_mdp_sspp_fetch_type {