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Commit 7cfa5245 authored by Yan He's avatar Yan He
Browse files

msm: ep_pcie: correct PME configuration 



Correct the PME configuration for PCIe endpoint to support D0, D3
hot and D3 cold.

Change-Id: Ib906fbafc490be75e5f178176e33882c392d074e
Signed-off-by: default avatarYan He <yanhe@codeaurora.org>
parent 75b675a3

drivers/platform/msm/ep_pcie/ep_pcie_core.c

+1 −1
Original line number Diff line number Diff line
@@ -510,7 +510,7 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev) 


	/* Set the PMC Register - to support PME in D0, D3hot and D3cold */

	ep_pcie_write_mask(dev->dm_core + PCIE20_CAP_ID_NXT_PTR, 0,

						BIT(4)|BIT(3)|BIT(0));

						BIT(31)|BIT(30)|BIT(27));



	/* Set the Endpoint L0s Acceptable Latency to 1us (max) */

	ep_pcie_write_reg_field(dev->dm_core, PCIE20_DEVICE_CAPABILITIES,