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Commit 7c6d87ac authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'viafb-next' of git://git.lwn.net/linux-2.6 

* 'viafb-next' of git://git.lwn.net/linux-2.6: (35 commits)
  viafb: move some include files to include/linux
  viafb: Eliminate some global.h references
  viafb: get rid of i2c debug cruft
  viafb: fold via_io.h into via-core.h
  viafb: Fix initialization error paths
  viafb: Do not remove gpiochip under spinlock
  viafb: make procfs entries optional
  viafb: fix proc entry removal
  viafb: improve misc register handling
  viafb: replace inb/outb
  viafb: move some modesetting functions to a seperate file
  viafb: unify modesetting functions
  viafb: Reserve framebuffer memory for the upcoming camera driver
  viafb: Add a simple VX855 DMA engine driver
  viafb: Add a simple interrupt management infrastructure
  via: Rationalize vt1636 detection
  viafb: Introduce viafb_find_i2c_adapter()
  via: Do not attempt I/O on inactive I2C adapters
  viafb: Turn GPIO and i2c into proper platform devices
  viafb: Convert GPIO and i2c to the new indexed port ops
  ...
parents a0fe3cc5 ec66841e

drivers/video/Kconfig

+16 −0
Original line number Diff line number Diff line
@@ -1511,6 +1511,7 @@ config FB_VIA 
       select FB_CFB_IMAGEBLIT

       select I2C_ALGOBIT

       select I2C

       select GPIOLIB

       help

	  This is the frame buffer device driver for Graphics chips of VIA

	  UniChrome (Pro) Family (CLE266,PM800/CN400,P4M800CE/P4M800Pro/
@@ -1520,6 +1521,21 @@ config FB_VIA 


	  To compile this driver as a module, choose M here: the

	  module will be called viafb.



if FB_VIA



config FB_VIA_DIRECT_PROCFS

	bool "direct hardware access via procfs (DEPRECATED)(DANGEROUS)"

	depends on FB_VIA

	default n

	help

	  Allow direct hardware access to some output registers via procfs.

	  This is dangerous but may provide the only chance to get the

	  correct output device configuration.

	  Its use is strongly discouraged.



endif



config FB_NEOMAGIC

	tristate "NeoMagic display support"

	depends on FB && PCI

drivers/video/via/Makefile

+3 −1
Original line number Diff line number Diff line
@@ -4,4 +4,6 @@ 


obj-$(CONFIG_FB_VIA) += viafb.o



viafb-y	:=viafbdev.o hw.o via_i2c.o dvi.o lcd.o ioctl.o accel.o via_utility.o vt1636.o global.o tblDPASetting.o viamode.o tbl1636.o
 
viafb-y	:=viafbdev.o hw.o via_i2c.o dvi.o lcd.o ioctl.o accel.o \

	via_utility.o vt1636.o global.o tblDPASetting.o viamode.o tbl1636.o \

	via-core.o via-gpio.o via_modesetting.o

drivers/video/via/accel.c

+91 −46
Original line number Diff line number Diff line
@@ -18,14 +18,45 @@ 
 * Foundation, Inc.,

 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.

 */

#include <linux/via-core.h>

#include "global.h"



/*

 * Figure out an appropriate bytes-per-pixel setting.

 */

static int viafb_set_bpp(void __iomem *engine, u8 bpp)

{

	u32 gemode;



	/* Preserve the reserved bits */

	/* Lowest 2 bits to zero gives us no rotation */

	gemode = readl(engine + VIA_REG_GEMODE) & 0xfffffcfc;

	switch (bpp) {

	case 8:

		gemode |= VIA_GEM_8bpp;

		break;

	case 16:

		gemode |= VIA_GEM_16bpp;

		break;

	case 32:

		gemode |= VIA_GEM_32bpp;

		break;

	default:

		printk(KERN_WARNING "viafb_set_bpp: Unsupported bpp %d\n", bpp);

		return -EINVAL;

	}

	writel(gemode, engine + VIA_REG_GEMODE);

	return 0;

}





static int hw_bitblt_1(void __iomem *engine, u8 op, u32 width, u32 height,

	u8 dst_bpp, u32 dst_addr, u32 dst_pitch, u32 dst_x, u32 dst_y,

	u32 *src_mem, u32 src_addr, u32 src_pitch, u32 src_x, u32 src_y,

	u32 fg_color, u32 bg_color, u8 fill_rop)

{

	u32 ge_cmd = 0, tmp, i;

	int ret;



	if (!op || op > 3) {

		printk(KERN_WARNING "hw_bitblt_1: Invalid operation: %d\n", op);
@@ -59,22 +90,9 @@ static int hw_bitblt_1(void __iomem *engine, u8 op, u32 width, u32 height, 
		}

	}



	switch (dst_bpp) {

	case 8:

		tmp = 0x00000000;

		break;

	case 16:

		tmp = 0x00000100;

		break;

	case 32:

		tmp = 0x00000300;

		break;

	default:

		printk(KERN_WARNING "hw_bitblt_1: Unsupported bpp %d\n",

			dst_bpp);

		return -EINVAL;

	}

	writel(tmp, engine + 0x04);

	ret = viafb_set_bpp(engine, dst_bpp);

	if (ret)

		return ret;



	if (op != VIA_BITBLT_FILL) {

		if (src_x & (op == VIA_BITBLT_MONO ? 0xFFFF8000 : 0xFFFFF000)
@@ -171,6 +189,7 @@ static int hw_bitblt_2(void __iomem *engine, u8 op, u32 width, u32 height, 
	u32 fg_color, u32 bg_color, u8 fill_rop)

{

	u32 ge_cmd = 0, tmp, i;

	int ret;



	if (!op || op > 3) {

		printk(KERN_WARNING "hw_bitblt_2: Invalid operation: %d\n", op);
@@ -204,22 +223,9 @@ static int hw_bitblt_2(void __iomem *engine, u8 op, u32 width, u32 height, 
		}

	}



	switch (dst_bpp) {

	case 8:

		tmp = 0x00000000;

		break;

	case 16:

		tmp = 0x00000100;

		break;

	case 32:

		tmp = 0x00000300;

		break;

	default:

		printk(KERN_WARNING "hw_bitblt_2: Unsupported bpp %d\n",

			dst_bpp);

		return -EINVAL;

	}

	writel(tmp, engine + 0x04);

	ret = viafb_set_bpp(engine, dst_bpp);

	if (ret)

		return ret;



	if (op == VIA_BITBLT_FILL)

		tmp = 0;
@@ -312,17 +318,29 @@ int viafb_init_engine(struct fb_info *info) 
{

	struct viafb_par *viapar = info->par;

	void __iomem *engine;

	int highest_reg, i;

	u32 vq_start_addr, vq_end_addr, vq_start_low, vq_end_low, vq_high,

		vq_len, chip_name = viapar->shared->chip_info.gfx_chip_name;



	engine = ioremap_nocache(info->fix.mmio_start, info->fix.mmio_len);

	viapar->shared->engine_mmio = engine;

	engine = viapar->shared->vdev->engine_mmio;

	if (!engine) {

		printk(KERN_WARNING "viafb_init_accel: ioremap failed, "

			"hardware acceleration disabled\n");

		return -ENOMEM;

	}



	/* Initialize registers to reset the 2D engine */

	switch (viapar->shared->chip_info.twod_engine) {

	case VIA_2D_ENG_M1:

		highest_reg = 0x5c;

		break;

	default:

		highest_reg = 0x40;

		break;

	}

	for (i = 0; i <= highest_reg; i += 4)

		writel(0x0, engine + i);



	switch (chip_name) {

	case UNICHROME_CLE266:

	case UNICHROME_K400:
@@ -352,13 +370,28 @@ int viafb_init_engine(struct fb_info *info) 
	viapar->shared->vq_vram_addr = viapar->fbmem_free;

	viapar->fbmem_used += VQ_SIZE;



	/* Init 2D engine reg to reset 2D engine */

	writel(0x0, engine + VIA_REG_KEYCONTROL);

#if defined(CONFIG_FB_VIA_CAMERA) || defined(CONFIG_FB_VIA_CAMERA_MODULE)

	/*

	 * Set aside a chunk of framebuffer memory for the camera

	 * driver.  Someday this driver probably needs a proper allocator

	 * for fbmem; for now, we just have to do this before the

	 * framebuffer initializes itself.

	 *

	 * As for the size: the engine can handle three frames,

	 * 16 bits deep, up to VGA resolution.

	 */

	viapar->shared->vdev->camera_fbmem_size = 3*VGA_HEIGHT*VGA_WIDTH*2;

	viapar->fbmem_free -= viapar->shared->vdev->camera_fbmem_size;

	viapar->fbmem_used += viapar->shared->vdev->camera_fbmem_size;

	viapar->shared->vdev->camera_fbmem_offset = viapar->fbmem_free;

#endif



	/* Init AGP and VQ regs */

	switch (chip_name) {

	case UNICHROME_K8M890:

	case UNICHROME_P4M900:

	case UNICHROME_VX800:

	case UNICHROME_VX855:

		writel(0x00100000, engine + VIA_REG_CR_TRANSET);

		writel(0x680A0000, engine + VIA_REG_CR_TRANSPACE);

		writel(0x02000000, engine + VIA_REG_CR_TRANSPACE);
@@ -393,6 +426,8 @@ int viafb_init_engine(struct fb_info *info) 
	switch (chip_name) {

	case UNICHROME_K8M890:

	case UNICHROME_P4M900:

	case UNICHROME_VX800:

	case UNICHROME_VX855:

		vq_start_low |= 0x20000000;

		vq_end_low |= 0x20000000;

		vq_high |= 0x20000000;
@@ -446,7 +481,7 @@ void viafb_show_hw_cursor(struct fb_info *info, int Status) 
	struct viafb_par *viapar = info->par;

	u32 temp, iga_path = viapar->iga_path;



	temp = readl(viapar->shared->engine_mmio + VIA_REG_CURSOR_MODE);

	temp = readl(viapar->shared->vdev->engine_mmio + VIA_REG_CURSOR_MODE);

	switch (Status) {

	case HW_Cursor_ON:

		temp |= 0x1;
@@ -463,23 +498,33 @@ void viafb_show_hw_cursor(struct fb_info *info, int Status) 
	default:

		temp &= 0x7FFFFFFF;

	}

	writel(temp, viapar->shared->engine_mmio + VIA_REG_CURSOR_MODE);

	writel(temp, viapar->shared->vdev->engine_mmio + VIA_REG_CURSOR_MODE);

}



void viafb_wait_engine_idle(struct fb_info *info)

{

	struct viafb_par *viapar = info->par;

	int loop = 0;



	while (!(readl(viapar->shared->engine_mmio + VIA_REG_STATUS) &

	u32 mask;

	void __iomem *engine = viapar->shared->vdev->engine_mmio;



	switch (viapar->shared->chip_info.twod_engine) {

	case VIA_2D_ENG_H5:

	case VIA_2D_ENG_M1:

		mask = VIA_CMD_RGTR_BUSY_M1 | VIA_2D_ENG_BUSY_M1 |

			      VIA_3D_ENG_BUSY_M1;

		break;

	default:

		while (!(readl(engine + VIA_REG_STATUS) &

				VIA_VR_QUEUE_BUSY) && (loop < MAXLOOP)) {

			loop++;

			cpu_relax();

		}

		mask = VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY;

		break;

	}



	while ((readl(viapar->shared->engine_mmio + VIA_REG_STATUS) &

		    (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY)) &&

		    (loop < MAXLOOP)) {

	while ((readl(engine + VIA_REG_STATUS) & mask) && (loop < MAXLOOP)) {

		loop++;

		cpu_relax();

	}

drivers/video/via/accel.h

+40 −0
Original line number Diff line number Diff line
@@ -67,6 +67,34 @@ 
/* from 0x100 to 0x1ff */

#define VIA_REG_COLORPAT        0x100



/* defines for VIA 2D registers for vt3353/3409 (M1 engine)*/

#define VIA_REG_GECMD_M1        0x000

#define VIA_REG_GEMODE_M1       0x004

#define VIA_REG_GESTATUS_M1     0x004       /* as same as VIA_REG_GEMODE */

#define VIA_REG_PITCH_M1        0x008       /* pitch of src and dst */

#define VIA_REG_DIMENSION_M1    0x00C       /* width and height */

#define VIA_REG_DSTPOS_M1       0x010

#define VIA_REG_LINE_XY_M1      0x010

#define VIA_REG_DSTBASE_M1      0x014

#define VIA_REG_SRCPOS_M1       0x018

#define VIA_REG_LINE_K1K2_M1    0x018

#define VIA_REG_SRCBASE_M1      0x01C

#define VIA_REG_PATADDR_M1      0x020

#define VIA_REG_MONOPAT0_M1     0x024

#define VIA_REG_MONOPAT1_M1     0x028

#define VIA_REG_OFFSET_M1       0x02C

#define VIA_REG_LINE_ERROR_M1   0x02C

#define VIA_REG_CLIPTL_M1       0x040       /* top and left of clipping */

#define VIA_REG_CLIPBR_M1       0x044       /* bottom and right of clipping */

#define VIA_REG_KEYCONTROL_M1   0x048       /* color key control */

#define VIA_REG_FGCOLOR_M1      0x04C

#define VIA_REG_DSTCOLORKEY_M1  0x04C       /* as same as VIA_REG_FG */

#define VIA_REG_BGCOLOR_M1      0x050

#define VIA_REG_SRCCOLORKEY_M1  0x050       /* as same as VIA_REG_BG */

#define VIA_REG_MONOPATFGC_M1   0x058       /* Add BG color of Pattern. */

#define VIA_REG_MONOPATBGC_M1   0x05C       /* Add FG color of Pattern. */

#define VIA_REG_COLORPAT_M1     0x100       /* from 0x100 to 0x1ff */



/* VIA_REG_PITCH(0x38): Pitch Setting */

#define VIA_PITCH_ENABLE        0x80000000
@@ -157,6 +185,18 @@ 
/* Virtual Queue is busy */

#define VIA_VR_QUEUE_BUSY       0x00020000



/* VIA_REG_STATUS(0x400): Engine Status for H5 */

#define VIA_CMD_RGTR_BUSY_H5   0x00000010  /* Command Regulator is busy */

#define VIA_2D_ENG_BUSY_H5     0x00000002  /* 2D Engine is busy */

#define VIA_3D_ENG_BUSY_H5     0x00001FE1  /* 3D Engine is busy */

#define VIA_VR_QUEUE_BUSY_H5   0x00000004  /* Virtual Queue is busy */



/* VIA_REG_STATUS(0x400): Engine Status for VT3353/3409 */

#define VIA_CMD_RGTR_BUSY_M1   0x00000010  /* Command Regulator is busy */

#define VIA_2D_ENG_BUSY_M1     0x00000002  /* 2D Engine is busy */

#define VIA_3D_ENG_BUSY_M1     0x00001FE1  /* 3D Engine is busy */

#define VIA_VR_QUEUE_BUSY_M1   0x00000004  /* Virtual Queue is busy */



#define MAXLOOP                 0xFFFFFF



#define VIA_BITBLT_COLOR	1

drivers/video/via/chip.h

+8 −0
Original line number Diff line number Diff line
@@ -121,9 +121,17 @@ struct lvds_chip_information { 
	int i2c_port;

};



/* The type of 2D engine */

enum via_2d_engine {

	VIA_2D_ENG_H2,

	VIA_2D_ENG_H5,

	VIA_2D_ENG_M1,

};



struct chip_information {

	int gfx_chip_name;

	int gfx_chip_revision;

	enum via_2d_engine twod_engine;

	struct tmds_chip_information tmds_chip_info;

	struct lvds_chip_information lvds_chip_info;

	struct lvds_chip_information lvds_chip_info2;