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Commit 7c68a08a authored by Subhash Jadavani's avatar Subhash Jadavani
Browse files

ARM: dts: msm: remove unnecessary UFS clocks for 8996 v2 & v3 



gcc_ufs_sys_clk_core_clk & gcc_ufs_tx_symbol_clk_core_clk are required
only for 8996 v1, this change removes the voting for these clocks on
v2 & v3.

Change-Id: Ie3e3c963acad10266d4e1688455347d3f8d78372
Signed-off-by: default avatarSubhash Jadavani <subhashj@codeaurora.org>
parent 861a4ae9

arch/arm/boot/dts/qcom/msm8996-v1.dtsi

+45 −0
Original line number Diff line number Diff line
@@ -118,3 +118,48 @@ 
		maximum-speed = "high-speed";

	};

};



&ufs1 {

	clock-names =

		"core_clk_src",

		"core_clk",

		"bus_clk",

		"bus_aggr_clk",

		"iface_clk",

		"core_clk_unipro_src",

		"core_clk_unipro",

		"core_clk_ice",

		"ref_clk",

		"tx_lane0_sync_clk",

		"rx_lane0_sync_clk",

		"sys_clk_core_clk",

		"tx_symbol_clk_core_clk";

	clocks =

		<&clock_gcc clk_ufs_axi_clk_src>,

		<&clock_gcc clk_gcc_ufs_axi_clk>,

		<&clock_gcc clk_gcc_sys_noc_ufs_axi_clk>,

		<&clock_gcc clk_gcc_aggre2_ufs_axi_clk>,

		<&clock_gcc clk_gcc_ufs_ahb_clk>,

		<&clock_gcc clk_ufs_ice_core_clk_src>,

		<&clock_gcc clk_gcc_ufs_unipro_core_clk>,

		<&clock_gcc clk_gcc_ufs_ice_core_clk>,

		<&clock_gcc clk_bb_clk1>,

		<&clock_gcc clk_gcc_ufs_tx_symbol_0_clk>,

		<&clock_gcc clk_gcc_ufs_rx_symbol_0_clk>,

		<&clock_gcc clk_gcc_ufs_sys_clk_core_clk>,

		<&clock_gcc clk_gcc_ufs_tx_symbol_clk_core_clk>;

	freq-table-hz =

		<100000000 200000000>,

		<0 0>,

		<0 0>,

		<0 0>,

		<0 0>,

		<150000000 300000000>,

		<0 0>,

		<0 0>,

		<0 0>,

		<0 0>,

		<0 0>,

		<0 0>,

		<0 0>;

};

arch/arm/boot/dts/qcom/msm8996.dtsi

+2 −8
Original line number Diff line number Diff line
@@ -1278,9 +1278,7 @@ 
			"core_clk_ice",

			"ref_clk",

			"tx_lane0_sync_clk",

			"rx_lane0_sync_clk",

			"sys_clk_core_clk",

			"tx_symbol_clk_core_clk";

			"rx_lane0_sync_clk";

		clocks =

			<&clock_gcc clk_ufs_axi_clk_src>,

			<&clock_gcc clk_gcc_ufs_axi_clk>,
@@ -1292,9 +1290,7 @@ 
			<&clock_gcc clk_gcc_ufs_ice_core_clk>,

			<&clock_gcc clk_bb_clk1>,

			<&clock_gcc clk_gcc_ufs_tx_symbol_0_clk>,

			<&clock_gcc clk_gcc_ufs_rx_symbol_0_clk>,

			<&clock_gcc clk_gcc_ufs_sys_clk_core_clk>,

			<&clock_gcc clk_gcc_ufs_tx_symbol_clk_core_clk>;

			<&clock_gcc clk_gcc_ufs_rx_symbol_0_clk>;

		freq-table-hz =

			<100000000 200000000>,

			<0 0>,
@@ -1306,8 +1302,6 @@ 
			<0 0>,

			<0 0>,

			<0 0>,

			<0 0>,

			<0 0>,

			<0 0>;



		lanes-per-direction = <1>;