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Commit 7c4b24da authored by Manuel Lauss's avatar Manuel Lauss Committed by Ralf Baechle
Browse files

MIPS: Alchemy: merge devboard code into single per-board files. 



Signed-off-by: default avatarManuel Lauss <manuel.lauss@googlemail.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2884/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 8e026910

arch/mips/alchemy/devboards/Makefile

+8 −8
Original line number Diff line number Diff line
@@ -4,13 +4,13 @@ 


obj-y += prom.o bcsr.o platform.o

obj-$(CONFIG_PM)		+= pm.o

obj-$(CONFIG_MIPS_PB1100)	+= pb1100/

obj-$(CONFIG_MIPS_PB1200)	+= pb1200/

obj-$(CONFIG_MIPS_PB1500)	+= pb1500/

obj-$(CONFIG_MIPS_PB1550)	+= pb1550/

obj-$(CONFIG_MIPS_DB1000)	+= db1x00/

obj-$(CONFIG_MIPS_DB1100)	+= db1x00/

obj-$(CONFIG_MIPS_DB1200)	+= db1200/

obj-$(CONFIG_MIPS_PB1100)	+= pb1100.o

obj-$(CONFIG_MIPS_PB1200)	+= pb1200.o

obj-$(CONFIG_MIPS_PB1500)	+= pb1500.o

obj-$(CONFIG_MIPS_PB1550)	+= pb1550.o

obj-$(CONFIG_MIPS_DB1000)	+= db1x00.o

obj-$(CONFIG_MIPS_DB1100)	+= db1x00.o

obj-$(CONFIG_MIPS_DB1200)	+= db1200.o

obj-$(CONFIG_MIPS_DB1300)	+= db1300.o

obj-$(CONFIG_MIPS_DB1500)	+= db1x00/

obj-$(CONFIG_MIPS_DB1500)	+= db1x00.o

obj-$(CONFIG_MIPS_DB1550)	+= db1550.o

arch/mips/alchemy/devboards/db1200/platform.c→arch/mips/alchemy/devboards/db1200.c

+76 −19
Original line number Diff line number Diff line 
/*

 * DBAu1200 board platform device registration

 *

 * Copyright (C) 2008-2009 Manuel Lauss

 * Copyright (C) 2008-2011 Manuel Lauss

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by
@@ -22,6 +22,7 @@ 
#include <linux/gpio.h>

#include <linux/i2c.h>

#include <linux/init.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/leds.h>

#include <linux/mmc/host.h>
@@ -33,14 +34,64 @@ 
#include <linux/spi/spi.h>

#include <linux/spi/flash.h>

#include <linux/smc91x.h>



#include <asm/mach-au1x00/au1000.h>

#include <asm/mach-au1x00/au1100_mmc.h>

#include <asm/mach-au1x00/au1xxx_dbdma.h>

#include <asm/mach-au1x00/au1550_spi.h>

#include <asm/mach-db1x00/bcsr.h>

#include <asm/mach-db1x00/db1200.h>



#include "../platform.h"

#include "platform.h"





const char *get_system_type(void)

{

	return "DB1200";

}



void __init board_setup(void)

{

	unsigned long freq0, clksrc, div, pfc;

	unsigned short whoami;



	bcsr_init(DB1200_BCSR_PHYS_ADDR,

		  DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);



	whoami = bcsr_read(BCSR_WHOAMI);

	printk(KERN_INFO "Alchemy/AMD/RMI DB1200 Board, CPLD Rev %d"

		"  Board-ID %d  Daughtercard ID %d\n",

		(whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);



	/* SMBus/SPI on PSC0, Audio on PSC1 */

	pfc = __raw_readl((void __iomem *)SYS_PINFUNC);

	pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);

	pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);

	pfc |= SYS_PINFUNC_P1C;	/* SPI is configured later */

	__raw_writel(pfc, (void __iomem *)SYS_PINFUNC);

	wmb();



	/* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from

	 * CPU clock; all other clock generators off/unused.

	 */

	div = (get_au1x00_speed() + 25000000) / 50000000;

	if (div & 1)

		div++;

	div = ((div >> 1) - 1) & 0xff;



	freq0 = div << SYS_FC_FRDIV0_BIT;

	__raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);

	wmb();

	freq0 |= SYS_FC_FE0;	/* enable F0 */

	__raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);

	wmb();



	/* psc0_intclk comes 1:1 from F0 */

	clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT;

	__raw_writel(clksrc, (void __iomem *)SYS_CLKSRC);

	wmb();

}



/******************************************************************************/



static struct mtd_partition db1200_spiflash_parts[] = {

	{
@@ -78,18 +129,9 @@ static struct spi_board_info db1200_spi_devs[] __initdata = { 
};



static struct i2c_board_info db1200_i2c_devs[] __initdata = {

	{

		/* AT24C04-10 I2C eeprom */

		I2C_BOARD_INFO("24c04", 0x52),

	},

	{

		/* Philips NE1619 temp/voltage sensor (adm1025 drv) */

		I2C_BOARD_INFO("ne1619", 0x2d),

	},

	{

		/* I2S audio codec WM8731 */

		I2C_BOARD_INFO("wm8731", 0x1b),

	},

	{ I2C_BOARD_INFO("24c04", 0x52),  }, /* AT24C04-10 I2C eeprom */

	{ I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */

	{ I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec WM8731 */

};



/**********************************************************************/
@@ -221,13 +263,13 @@ static struct resource db1200_ide_res[] = { 
	},

};



static u64 ide_dmamask = DMA_BIT_MASK(32);

static u64 au1200_ide_dmamask = DMA_BIT_MASK(32);



static struct platform_device db1200_ide_dev = {

	.name		= "au1200-ide",

	.id		= 0,

	.dev = {

		.dma_mask 		= &ide_dmamask,

		.dma_mask		= &au1200_ide_dmamask,

		.coherent_dma_mask	= DMA_BIT_MASK(32),

	},

	.num_resources	= ARRAY_SIZE(db1200_ide_res),
@@ -533,6 +575,21 @@ static int __init db1200_dev_init(void) 
	unsigned short sw;

	int swapped;



	/* GPIO7 is low-level triggered CPLD cascade */

	irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);

	bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);



	/* insert/eject pairs: one of both is always screaming.  To avoid

	 * issues they must not be automatically enabled when initially

	 * requested.

	 */

	irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN);

	irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN);

	irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN);

	irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN);

	irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN);

	irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN);



	i2c_register_board_info(0, db1200_i2c_devs,

				ARRAY_SIZE(db1200_i2c_devs));

	spi_register_board_info(db1200_spi_devs,

arch/mips/alchemy/devboards/db1200/Makefile

deleted100644 → 0
+0 −1
Original line number Diff line number Diff line 
obj-y += setup.o platform.o

arch/mips/alchemy/devboards/db1200/setup.c

deleted100644 → 0
+0 −81
Original line number Diff line number Diff line 
/*

 * Alchemy/AMD/RMI DB1200 board setup.

 *

 * Licensed under the terms outlined in the file COPYING in the root of

 * this source archive.

 */



#include <linux/init.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/kernel.h>

#include <asm/mach-au1x00/au1000.h>

#include <asm/mach-db1x00/bcsr.h>

#include <asm/mach-db1x00/db1200.h>



const char *get_system_type(void)

{

	return "Alchemy Db1200";

}



void __init board_setup(void)

{

	unsigned long freq0, clksrc, div, pfc;

	unsigned short whoami;



	bcsr_init(DB1200_BCSR_PHYS_ADDR,

		  DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);



	whoami = bcsr_read(BCSR_WHOAMI);

	printk(KERN_INFO "Alchemy/AMD/RMI DB1200 Board, CPLD Rev %d"

		"  Board-ID %d  Daughtercard ID %d\n",

		(whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);



	/* SMBus/SPI on PSC0, Audio on PSC1 */

	pfc = __raw_readl((void __iomem *)SYS_PINFUNC);

	pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);

	pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);

	pfc |= SYS_PINFUNC_P1C;	/* SPI is configured later */

	__raw_writel(pfc, (void __iomem *)SYS_PINFUNC);

	wmb();



	/* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from

	 * CPU clock; all other clock generators off/unused.

	 */

	div = (get_au1x00_speed() + 25000000) / 50000000;

	if (div & 1)

		div++;

	div = ((div >> 1) - 1) & 0xff;



	freq0 = div << SYS_FC_FRDIV0_BIT;

	__raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);

	wmb();

	freq0 |= SYS_FC_FE0;	/* enable F0 */

	__raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);

	wmb();



	/* psc0_intclk comes 1:1 from F0 */

	clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT;

	__raw_writel(clksrc, (void __iomem *)SYS_CLKSRC);

	wmb();

}



static int __init db1200_arch_init(void)

{

	/* GPIO7 is low-level triggered CPLD cascade */

	irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);

	bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);



	/* insert/eject pairs: one of both is always screaming.  To avoid

	 * issues they must not be automatically enabled when initially

	 * requested.

	 */

	irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN);

	irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN);

	irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN);

	irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN);

	irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN);

	irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN);

	return 0;

}

arch_initcall(db1200_arch_init);

arch/mips/alchemy/devboards/db1x00/platform.c→arch/mips/alchemy/devboards/db1x00.c

+56 −7
Original line number Diff line number Diff line 
/*

 * DBAu1xxx board platform device registration

 * DBAu1000/1500/1100 board support

 *

 * Copyright (C) 2009 Manuel Lauss

 * Copyright 2000, 2008 MontaVista Software Inc.

 * Author: MontaVista Software, Inc. <source@mvista.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by
@@ -18,18 +19,59 @@ 
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

 */



#include <linux/dma-mapping.h>

#include <linux/gpio.h>

#include <linux/init.h>

#include <linux/interrupt.h>

#include <linux/dma-mapping.h>

#include <linux/platform_device.h>



#include <linux/pm.h>

#include <asm/mach-au1x00/au1000.h>

#include <asm/mach-au1x00/au1000_dma.h>

#include <asm/mach-db1x00/bcsr.h>

#include "../platform.h"

#include <asm/reboot.h>

#include <prom.h>

#include "platform.h"



struct pci_dev;



const char *get_system_type(void)

{

	return "Alchemy Db1x00";

}



void __init board_setup(void)

{

#ifdef CONFIG_MIPS_DB1000

	printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n");

#endif

#ifdef CONFIG_MIPS_DB1500

	printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n");

#endif

#ifdef CONFIG_MIPS_DB1100

	printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n");

#endif

	/* initialize board register space */

	bcsr_init(DB1000_BCSR_PHYS_ADDR,

		  DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);



#if defined(CONFIG_IRDA) && defined(CONFIG_AU1000_FIR)

	{

		u32 pin_func;



		/* Set IRFIRSEL instead of GPIO15 */

		pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF;

		au_writel(pin_func, SYS_PINFUNC);

		/* Power off until the driver is in use */

		bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK,

			 BCSR_RESETS_IRDA_MODE_OFF);

	}

#endif

	bcsr_write(BCSR_PCMCIA, 0);	/* turn off PCMCIA power */



	/* Enable GPIO[31:0] inputs */

	alchemy_gpio1_input_enable();

}



/* DB1xxx PCMCIA interrupt sources:

 * CD0/1	GPIO0/3

 * STSCHG0/1	GPIO1/4
@@ -174,6 +216,13 @@ static struct platform_device db1x00_audio_dev = { 


static int __init db1xxx_dev_init(void)

{

	irq_set_irq_type(DB1XXX_PCMCIA_CD0, IRQ_TYPE_EDGE_BOTH);

	irq_set_irq_type(DB1XXX_PCMCIA_CD1, IRQ_TYPE_EDGE_BOTH);

	irq_set_irq_type(DB1XXX_PCMCIA_CARD0, IRQ_TYPE_LEVEL_LOW);

	irq_set_irq_type(DB1XXX_PCMCIA_CARD1, IRQ_TYPE_LEVEL_LOW);

	irq_set_irq_type(DB1XXX_PCMCIA_STSCHG0, IRQ_TYPE_LEVEL_LOW);

	irq_set_irq_type(DB1XXX_PCMCIA_STSCHG1, IRQ_TYPE_LEVEL_LOW);



	db1x_register_pcmcia_socket(

		AU1000_PCMCIA_ATTR_PHYS_ADDR,

		AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
@@ -201,7 +250,7 @@ static int __init db1xxx_dev_init(void) 
	platform_device_register(&alchemy_ac97c_dev);

	platform_device_register(&db1x00_audio_dev);



	db1x_register_norflash(0x02000000, 4 /* 32bit */, F_SWAPPED);

	db1x_register_norflash(32 << 20, 4 /* 32bit */, F_SWAPPED);

	return 0;

}

device_initcall(db1xxx_dev_init);