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Commit 7bac6b46 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-fixes-3.6' of git://people.freedesktop.org/~agd5f/linux into drm-fixes 

Alex Deucher writes:
This is the current set of radeon fixes for 3.6.  Nothing too major.

Highlights:
- various display fixes
- some SI fixes
- new SI pci ids
- major VM fix
- CS checker support for MSAA

I've tested on a number of cards across generations and noticed no problems.

* 'drm-fixes-3.6' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon: fix typo in function header comment
  drm/radeon/kms: implement timestamp userspace query (v2)
  drm/radeon/kms: add MSAA texture support for r600-evergreen
  drm/radeon/kms: reorder code in r600_check_texture_resource
  drm/radeon: fence virtual address and free it once idle v4
  drm/radeon: fix some missing parens in asic macros
  drm/radeon: add some new SI pci ids
  drm/radeon: fix ordering in pll picking on dce4+
  drm/radeon: do not reenable crtc after moving vram start address
  drm/radeon: fix bank tiling parameters on cayman
  drm/radeon: fix bank tiling parameters on evergreen
  drm/radeon: fix bank tiling parameters on SI
  drm/radeon: properly handle crtc powergating
  drm/radeon: properly handle SS overrides on TN (v2)
  drm/radeon/dce4+: set a more reasonable cursor watermark
  drm/radeon: fix handling for ddc type 5 on combios
parents 9830605d f59abbf2

drivers/gpu/drm/radeon/atombios_crtc.c

+16 −6
Original line number Diff line number Diff line
@@ -259,7 +259,7 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) 
		/* adjust pm to dpms changes BEFORE enabling crtcs */

		radeon_pm_compute_clocks(rdev);

		/* disable crtc pair power gating before programming */

		if (ASIC_IS_DCE6(rdev))

		if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set)

			atombios_powergate_crtc(crtc, ATOM_DISABLE);

		atombios_enable_crtc(crtc, ATOM_ENABLE);

		if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
@@ -279,7 +279,7 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) 
		atombios_enable_crtc(crtc, ATOM_DISABLE);

		radeon_crtc->enabled = false;

		/* power gating is per-pair */

		if (ASIC_IS_DCE6(rdev)) {

		if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set) {

			struct drm_crtc *other_crtc;

			struct radeon_crtc *other_radeon_crtc;

			list_for_each_entry(other_crtc, &rdev->ddev->mode_config.crtc_list, head) {
@@ -1531,12 +1531,12 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) 
				 * crtc virtual pixel clock.

				 */

				if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {

					if (ASIC_IS_DCE5(rdev))

						return ATOM_DCPLL;

					if (rdev->clock.dp_extclk)

						return ATOM_PPLL_INVALID;

					else if (ASIC_IS_DCE6(rdev))

						return ATOM_PPLL0;

					else if (rdev->clock.dp_extclk)

						return ATOM_PPLL_INVALID;

					else if (ASIC_IS_DCE5(rdev))

						return ATOM_DCPLL;

				}

			}

		}
@@ -1635,18 +1635,28 @@ static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, 
static void atombios_crtc_prepare(struct drm_crtc *crtc)

{

	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

	struct drm_device *dev = crtc->dev;

	struct radeon_device *rdev = dev->dev_private;



	radeon_crtc->in_mode_set = true;

	/* pick pll */

	radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);



	/* disable crtc pair power gating before programming */

	if (ASIC_IS_DCE6(rdev))

		atombios_powergate_crtc(crtc, ATOM_DISABLE);



	atombios_lock_crtc(crtc, ATOM_ENABLE);

	atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);

}



static void atombios_crtc_commit(struct drm_crtc *crtc)

{

	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);



	atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);

	atombios_lock_crtc(crtc, ATOM_DISABLE);

	radeon_crtc->in_mode_set = false;

}



static void atombios_crtc_disable(struct drm_crtc *crtc)

drivers/gpu/drm/radeon/evergreen.c

+11 −60
Original line number Diff line number Diff line
@@ -1229,24 +1229,8 @@ void evergreen_agp_enable(struct radeon_device *rdev) 


void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)

{

	save->vga_control[0] = RREG32(D1VGA_CONTROL);

	save->vga_control[1] = RREG32(D2VGA_CONTROL);

	save->vga_render_control = RREG32(VGA_RENDER_CONTROL);

	save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);

	save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);

	save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);

	if (rdev->num_crtc >= 4) {

		save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);

		save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);

		save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);

		save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);

	}

	if (rdev->num_crtc >= 6) {

		save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);

		save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);

		save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);

		save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);

	}



	/* Stop all video */

	WREG32(VGA_RENDER_CONTROL, 0);
@@ -1357,47 +1341,6 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s 
	/* Unlock host access */

	WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);

	mdelay(1);

	/* Restore video state */

	WREG32(D1VGA_CONTROL, save->vga_control[0]);

	WREG32(D2VGA_CONTROL, save->vga_control[1]);

	if (rdev->num_crtc >= 4) {

		WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);

		WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);

	}

	if (rdev->num_crtc >= 6) {

		WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);

		WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);

	}

	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);

	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);

	if (rdev->num_crtc >= 4) {

		WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);

		WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);

	}

	if (rdev->num_crtc >= 6) {

		WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);

		WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);

	}

	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);

	WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);

	if (rdev->num_crtc >= 4) {

		WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);

		WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);

	}

	if (rdev->num_crtc >= 6) {

		WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);

		WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);

	}

	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);

	WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);

	if (rdev->num_crtc >= 4) {

		WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);

		WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);

	}

	if (rdev->num_crtc >= 6) {

		WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);

		WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);

	}

	WREG32(VGA_RENDER_CONTROL, save->vga_render_control);

}
@@ -1986,10 +1929,18 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 
	if (rdev->flags & RADEON_IS_IGP)

		rdev->config.evergreen.tile_config |= 1 << 4;

	else {

		if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)

			rdev->config.evergreen.tile_config |= 1 << 4;

		else

		switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {

		case 0: /* four banks */

			rdev->config.evergreen.tile_config |= 0 << 4;

			break;

		case 1: /* eight banks */

			rdev->config.evergreen.tile_config |= 1 << 4;

			break;

		case 2: /* sixteen banks */

		default:

			rdev->config.evergreen.tile_config |= 2 << 4;

			break;

		}

	}

	rdev->config.evergreen.tile_config |= 0 << 8;

	rdev->config.evergreen.tile_config |=

drivers/gpu/drm/radeon/evergreen_cs.c

+7 −0
Original line number Diff line number Diff line
@@ -788,6 +788,13 @@ static int evergreen_cs_track_validate_texture(struct radeon_cs_parser *p, 
	case V_030000_SQ_TEX_DIM_1D_ARRAY:

	case V_030000_SQ_TEX_DIM_2D_ARRAY:

		depth = 1;

		break;

	case V_030000_SQ_TEX_DIM_2D_MSAA:

	case V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA:

		surf.nsamples = 1 << llevel;

		llevel = 0;

		depth = 1;

		break;

	case V_030000_SQ_TEX_DIM_3D:

		break;

	default:

drivers/gpu/drm/radeon/ni.c

+11 −3
Original line number Diff line number Diff line
@@ -574,10 +574,18 @@ static void cayman_gpu_init(struct radeon_device *rdev) 
	if (rdev->flags & RADEON_IS_IGP)

		rdev->config.cayman.tile_config |= 1 << 4;

	else {

		if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)

			rdev->config.cayman.tile_config |= 1 << 4;

		else

		switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {

		case 0: /* four banks */

			rdev->config.cayman.tile_config |= 0 << 4;

			break;

		case 1: /* eight banks */

			rdev->config.cayman.tile_config |= 1 << 4;

			break;

		case 2: /* sixteen banks */

		default:

			rdev->config.cayman.tile_config |= 2 << 4;

			break;

		}

	}

	rdev->config.cayman.tile_config |=

		((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;

drivers/gpu/drm/radeon/r600.c

+20 −0
Original line number Diff line number Diff line
@@ -3789,3 +3789,23 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev) 
		WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);

	}

}



/**

 * r600_get_gpu_clock - return GPU clock counter snapshot

 *

 * @rdev: radeon_device pointer

 *

 * Fetches a GPU clock counter snapshot (R6xx-cayman).

 * Returns the 64 bit clock counter snapshot.

 */

uint64_t r600_get_gpu_clock(struct radeon_device *rdev)

{

	uint64_t clock;



	mutex_lock(&rdev->gpu_clock_mutex);

	WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);

	clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |

	        ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);

	mutex_unlock(&rdev->gpu_clock_mutex);

	return clock;

}