RDMA/ocrdma: Remove __packed

#ifndef __OCRDMA_ABI_H__

#define __OCRDMA_ABI_H__

/* user kernel communication data structures. */

struct ocrdma_alloc_ucontext_resp {

	u32 dev_id;

	u32 wqe_size;

	u32 dpp_wqe_size;

	u64 ah_tbl_page;

	u32 ah_tbl_len;

	u32 rsvd;

	u8 fw_ver[32];

	u32 rqe_size;

	u8 fw_ver[32];

	/* for future use/new features in progress */

	u64 rsvd1;

} __packed;

	u64 rsvd2;

};

/* user kernel communication data structures. */

struct ocrdma_alloc_pd_ureq {

	u64 rsvd1;

} __packed;

};

struct ocrdma_alloc_pd_uresp {

	u32 id;

	u32 dpp_page_addr_hi;

	u32 dpp_page_addr_lo;

	u64 rsvd1;

} __packed;

};

struct ocrdma_create_cq_ureq {

	u32 dpp_cq;

	u32 rsvd;

} __packed;

	u32 rsvd; /* pad */

};

#define MAX_CQ_PAGES 8

struct ocrdma_create_cq_uresp {

	u64 db_page_addr;

	u32 db_page_size;

	u32 phase_change;

	/* for future use/new features in progress */

	u64 rsvd1;

	u64 rsvd2;

} __packed;

};

#define MAX_QP_PAGES 8

#define MAX_UD_AV_PAGES 8

	u8 enable_dpp_cq;

	u8 rsvd;

	u16 dpp_cq_id;

	u32 rsvd1;

	u32 rsvd1;	/* pad */

};

struct ocrdma_create_qp_uresp {

	u16 qp_id;

	u16 sq_dbid;

	u16 rq_dbid;

	u16 resv0;

	u16 resv0;	/* pad */

	u32 sq_page_size;

	u32 rq_page_size;

	u32 num_sq_pages;

	u32 db_page_size;

	u32 dpp_credit;

	u32 dpp_offset;

	u32 rsvd1;

	u32 num_wqe_allocated;

	u32 num_rqe_allocated;

	u32 db_sq_offset;

	u32 db_rq_offset;

	u32 db_shift;

	u64 rsvd1;

	u64 rsvd2;

	u64 rsvd3;

} __packed;

struct ocrdma_create_srq_uresp {

	u16 rq_dbid;

	u16 resv0;

	u16 resv0;	/* pad */

	u32 resv1;

	u32 rq_page_size;

	u64 rsvd2;

	u64 rsvd3;

} __packed;

};

#endif				/* __OCRDMA_ABI_H__ */

	u32 timeout;		/* in seconds */

	u32 cmd_len;

	u32 rsvd_version;

} __packed;

};

enum {

	OCRDMA_MBX_RSP_OPCODE_SHIFT	= 0,

	u32 status;

	u32 rsp_len;

	u32 add_rsp_len;

} __packed;

};

enum {

	OCRDMA_MQE_EMBEDDED	= 1,

	u32 pa_lo;

	u32 pa_hi;

	u32 len;

} __packed;

};

enum {

	OCRDMA_MQE_HDR_EMB_SHIFT	= 0,

	u32 tag_lo;

	u32 tag_hi;

	u32 rsvd3;

} __packed;

};

struct ocrdma_mqe_emb_cmd {

	struct ocrdma_mbx_hdr mch;

	u8 pyld[220];

} __packed;

};

struct ocrdma_mqe {

	struct ocrdma_mqe_hdr hdr;

		u8 cmd[236];

		struct ocrdma_mbx_rsp rsp;

	} u;

} __packed;

};

#define OCRDMA_EQ_LEN       4096

#define OCRDMA_MQ_CQ_LEN    256

struct ocrdma_delete_q_req {

	struct ocrdma_mbx_hdr req;

	u32 id;

} __packed;

};

struct ocrdma_pa {

	u32 lo;

	u32 hi;

} __packed;

};

#define MAX_OCRDMA_EQ_PAGES (8)

struct ocrdma_create_eq_req {

	u32 delay;

	u32 rsvd;

	struct ocrdma_pa pa[MAX_OCRDMA_EQ_PAGES];

} __packed;

};

enum {

	OCRDMA_CREATE_EQ_VALID	= Bit(29),

	u32 tag_lo;

	u32 tag_hi;

	u32 valid_ae_cmpl_cons;

} __packed;

};

enum {

	OCRDMA_AE_MCQE_QPVALID		= Bit(31),

	u32 cqvalid_cqid;

	u32 evt_tag;

	u32 valid_ae_event;

} __packed;

};

enum {

	OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT		= 16,

	u32 w1;

	u32 w2;

	u32 valid_ae_event;

} __packed;

};

enum {

	OCRDMA_AE_QP_MCQE_NEW_QP_STATE_SHIFT	= 0,

	u32 w1;

	u32 w2;

	u32 valid_ae_event;

} __packed;

};

#define OCRDMA_ASYNC_EVE_CODE 0x14

	u32 max_ird_ord_per_qp;

	u32 max_shared_ird_ord;

	u32 max_mr;

	u64 max_mr_size;

	u32 max_mr_size_lo;

	u32 max_mr_size_hi;

	u32 max_num_mr_pbl;

	u32 max_mw;

	u32 max_fmr;

	u32 max_wqes_rqes_per_q;

	u32 max_cq_cqes_per_cq;

	u32 max_srq_rqe_sge;

} __packed;

};

struct ocrdma_fw_ver_rsp {

	struct ocrdma_mqe_hdr hdr;

	struct ocrdma_mbx_rsp rsp;

	u8 running_ver[32];

} __packed;

};

struct ocrdma_fw_conf_rsp {

	struct ocrdma_mqe_hdr hdr;

	u32 base_eqid;

	u32 max_eq;

} __packed;

};

enum {

	OCRDMA_FN_MODE_RDMA	= 0x4

struct ocrdma_create_cq {

	struct ocrdma_mqe_hdr hdr;

	struct ocrdma_create_cq_cmd cmd;

} __packed;

};

enum {

	OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK	= 0xFFFF

struct ocrdma_create_cq_cmd_rsp {

	struct ocrdma_mbx_rsp rsp;

	u32 cq_id;

} __packed;

};

struct ocrdma_create_cq_rsp {

	struct ocrdma_mqe_hdr hdr;

	struct ocrdma_create_cq_cmd_rsp rsp;

} __packed;

};

enum {

	OCRDMA_CREATE_MQ_V0_CQ_ID_SHIFT		= 22,

	u32 async_cqid_valid;

	u32 rsvd;

	struct ocrdma_pa pa[8];

} __packed;

};

struct ocrdma_create_mq_rsp {

	struct ocrdma_mbx_rsp rsp;

	u32 id;

} __packed;

};

enum {

	OCRDMA_DESTROY_CQ_QID_SHIFT			= 0,

	struct ocrdma_mbx_hdr req;

	u32 bypass_flush_qid;

} __packed;

};

struct ocrdma_destroy_cq_rsp {

	struct ocrdma_mqe_hdr hdr;

	struct ocrdma_mbx_rsp rsp;

} __packed;

};

enum {

	OCRDMA_QPT_GSI	= 1,

	u32 dpp_credits_cqid;

	u32 rpir_lkey;

	struct ocrdma_pa ird_addr[MAX_OCRDMA_IRD_PAGES];

} __packed;

};

enum {

	OCRDMA_CREATE_QP_RSP_QP_ID_SHIFT		= 0,

	u32 max_ord_ird;

	u32 sq_rq_id;

	u32 dpp_response;

} __packed;

};

struct ocrdma_destroy_qp {

	struct ocrdma_mqe_hdr hdr;

	struct ocrdma_mbx_hdr req;

	u32 qp_id;

} __packed;

};

struct ocrdma_destroy_qp_rsp {

	struct ocrdma_mqe_hdr hdr;

	struct ocrdma_mbx_rsp rsp;

} __packed;

};

enum {

	OCRDMA_MODIFY_QP_ID_SHIFT	= 0,

	u32 dmac_b0_to_b3;

	u32 vlan_dmac_b4_to_b5;

	u32 qkey;

} __packed;

};

struct ocrdma_modify_qp {

	u32 flags;

	u32 rdma_flags;

	u32 num_outstanding_atomic_rd;

} __packed;

};

enum {

	OCRDMA_MODIFY_QP_RSP_MAX_RQE_SHIFT	= 0,

	u32 max_wqe_rqe;

	u32 max_ord_ird;

} __packed;

};

struct ocrdma_query_qp {

	struct ocrdma_mqe_hdr hdr;

#define OCRDMA_QUERY_UP_QP_ID_SHIFT 0

#define OCRDMA_QUERY_UP_QP_ID_MASK   0xFFFFFF

	u32 qp_id;

} __packed;

};

struct ocrdma_query_qp_rsp {

	struct ocrdma_mqe_hdr hdr;

	struct ocrdma_mbx_rsp rsp;

	struct ocrdma_qp_params params;

} __packed;

};

enum {

	OCRDMA_CREATE_SRQ_PD_ID_SHIFT		= 0,

	u32 max_sge_rqe;

	u32 pages_rqe_sz;

	struct ocrdma_pa rq_addr[MAX_OCRDMA_SRQ_PAGES];

} __packed;

};

enum {

	OCRDMA_CREATE_SRQ_RSP_SRQ_ID_SHIFT			= 0,

	u32 id;

	u32 max_sge_rqe_allocated;

} __packed;

};

enum {

	OCRDMA_MODIFY_SRQ_ID_SHIFT	= 0,

	u32 id;

	u32 limit_max_rqe;

} __packed;

};

enum {

	OCRDMA_QUERY_SRQ_ID_SHIFT	= 0,

	struct ocrdma_mbx_rsp req;

	u32 id;

} __packed;

};

enum {

	OCRDMA_QUERY_SRQ_RSP_PD_ID_SHIFT	= 0,

	u32 max_rqe_pdid;

	u32 srq_lmt_max_sge;

} __packed;

};

enum {

	OCRDMA_DESTROY_SRQ_ID_SHIFT	= 0,

	struct ocrdma_mbx_rsp req;

	u32 id;

} __packed;

};

enum {

	OCRDMA_ALLOC_PD_ENABLE_DPP	= BIT(16),

	struct ocrdma_mqe_hdr hdr;

	struct ocrdma_mbx_hdr req;

	u32 enable_dpp_rsvd;

} __packed;

};

enum {

	OCRDMA_ALLOC_PD_RSP_DPP			= Bit(16),

	struct ocrdma_mqe_hdr hdr;

	struct ocrdma_mbx_rsp rsp;

	u32 dpp_page_pdid;

} __packed;

};

struct ocrdma_dealloc_pd {

	struct ocrdma_mqe_hdr hdr;

	struct ocrdma_mbx_hdr req;

	u32 id;

} __packed;

};

struct ocrdma_dealloc_pd_rsp {

	struct ocrdma_mqe_hdr hdr;

	struct ocrdma_mbx_rsp rsp;

} __packed;

};

enum {

	OCRDMA_ADDR_CHECK_ENABLE	= 1,

	u32 pdid;

	u32 pbl_sz_flags;

} __packed;

};

struct ocrdma_alloc_lkey_rsp {

	struct ocrdma_mqe_hdr hdr;

	u32 lrkey;

	u32 num_pbl_rsvd;

} __packed;

};

struct ocrdma_dealloc_lkey {

	struct ocrdma_mqe_hdr hdr;

	u32 lkey;

	u32 rsvd_frmr;

} __packed;

};

struct ocrdma_dealloc_lkey_rsp {

	struct ocrdma_mqe_hdr hdr;

	struct ocrdma_mbx_rsp rsp;

} __packed;

};

#define MAX_OCRDMA_NSMR_PBL    (u32)22

#define MAX_OCRDMA_PBL_SIZE     65536

	u32 va_loaddr;

	u32 va_hiaddr;

	struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL];

} __packed;

};

enum {

	OCRDMA_REG_NSMR_CONT_PBL_SHIFT		= 0,

struct ocrdma_pbe {

	u32 pa_hi;

	u32 pa_lo;

} __packed;

};

enum {

	OCRDMA_REG_NSMR_RSP_NUM_PBL_SHIFT	= 16,

	u32 lrkey;

	u32 num_pbl;

} __packed;

};

enum {

	OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_SHIFT	= 0,

	u32 lrkey_key_index;

	u32 num_pbl;

} __packed;

};

enum {

	OCRDMA_ALLOC_MW_PD_ID_SHIFT	= 0,

	struct ocrdma_mbx_hdr req;

	u32 pdid;

} __packed;

};

enum {

	OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_SHIFT	= 0,

	struct ocrdma_mbx_rsp rsp;

	u32 lrkey_index;

} __packed;

};

struct ocrdma_attach_mcast {

	struct ocrdma_mqe_hdr hdr;

	u8 mgid[16];

	u32 mac_b0_to_b3;

	u32 vlan_mac_b4_to_b5;

} __packed;

};

struct ocrdma_attach_mcast_rsp {

	struct ocrdma_mqe_hdr hdr;

	struct ocrdma_mbx_rsp rsp;

} __packed;

};

struct ocrdma_detach_mcast {

	struct ocrdma_mqe_hdr hdr;

	u8 mgid[16];

	u32 mac_b0_to_b3;

	u32 vlan_mac_b4_to_b5;

} __packed;

};

struct ocrdma_detach_mcast_rsp {

	struct ocrdma_mqe_hdr hdr;

	struct ocrdma_mbx_rsp rsp;

} __packed;

};

enum {

	OCRDMA_CREATE_AH_NUM_PAGES_SHIFT	= 19,

	u32 ah_conf;

	struct ocrdma_pa tbl_addr[8];

} __packed;

};

struct ocrdma_create_ah_tbl_rsp {

	struct ocrdma_mqe_hdr hdr;

	struct ocrdma_mbx_rsp rsp;

	u32 ahid;

} __packed;

};

struct ocrdma_delete_ah_tbl {

	struct ocrdma_mqe_hdr hdr;

	struct ocrdma_mbx_hdr req;

	u32 ahid;

} __packed;

};

struct ocrdma_delete_ah_tbl_rsp {

	struct ocrdma_mqe_hdr hdr;

	struct ocrdma_mbx_rsp rsp;

} __packed;

};

enum {

	OCRDMA_EQE_VALID_SHIFT		= 0,

struct ocrdma_eqe {

	u32 id_valid;

} __packed;

};

enum OCRDMA_CQE_STATUS {

	OCRDMA_CQE_SUCCESS = 0,

		} cmn;

	};

	u32 flags_status_srcqpn;	/* w3 */

} __packed;

};

struct ocrdma_sge {

	u32 addr_hi;

	u32 addr_lo;

	u32 lrkey;

	u32 len;

} __packed;

};

enum {

	OCRDMA_FLAG_SIG		= 0x1,

		u32 lkey;

	};

	u32 total_len;

} __packed;

};

struct ocrdma_ewqe_ud_hdr {

	u32 rsvd_dest_qpn;

	u32 qkey;

	u32 rsvd_ahid;

	u32 rsvd;

} __packed;

};

struct ocrdma_eth_basic {

	u8 dmac[6];